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35b31f7c64
These don't seem to change at runtime, and the initialisers are constant data. This could be improved by not selecting the apu/non-apu path on each pcie read/write access. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
49 lines
2.3 KiB
C
49 lines
2.3 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __NBIO_V7_0_H__
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#define __NBIO_V7_0_H__
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#include "soc15_common.h"
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extern struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
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extern const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
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int nbio_v7_0_init(struct amdgpu_device *adev);
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u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
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uint32_t idx);
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void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev,
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uint32_t idx, uint32_t val);
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void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable);
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void nbio_v7_0_hdp_flush(struct amdgpu_device *adev);
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u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev);
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void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
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bool use_doorbell, int doorbell_index);
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void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
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bool enable);
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void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
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bool use_doorbell, int doorbell_index);
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void nbio_v7_0_ih_control(struct amdgpu_device *adev);
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u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev);
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void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable);
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#endif
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