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The CS4234 is a highly versatile CODEC that combines 4 channels of high performance analog to digital conversion, 4 channels of high performance digital to analog conversion for audio, and 1 channel of digital to analog conversion to provide a nondelayed audio reference signal to an external Class H tracking power supply. DAC5 is only supported as a 5th audio channel. Tracking Power Supply mode is not currently supported by the driver. In DSP_A mode the slots for DAC1-4 and optionally DAC5 can be set. The codec always claims 4 slots for DAC1-4 and these must be in the same nibble of the mask. The codec has a fixed mapping for ADC slots. In I2S/LJ modes the codec has a fixed mapping for DAC1-4 and ADC1-4. DAC5 is not available in these modes. The MCLK source must be preset to a valid frequency before probe() because it must be running all the time the codec is out of reset. The VA_SEL bit will be set automatically to 3.3v or 5v during probe() based on the reported voltage of the regulator supplying VA. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://lore.kernel.org/r/20200928111821.26967-2-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
287 lines
8.3 KiB
C
287 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ALSA SoC Audio driver for CS4234 codec
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*
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* Copyright (C) 2020 Cirrus Logic, Inc. and
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* Cirrus Logic International Semiconductor Ltd.
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*/
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#ifndef CS4234_H
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#define CS4234_H
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#define CS4234_DEVID_AB 0x01
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#define CS4234_DEVID_CD 0x02
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#define CS4234_DEVID_EF 0x03
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#define CS4234_REVID 0x05
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#define CS4234_CLOCK_SP 0x06
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#define CS4234_BASE_RATE_MASK 0xC0
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#define CS4234_BASE_RATE_SHIFT 6
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#define CS4234_SPEED_MODE_MASK 0x30
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#define CS4234_SPEED_MODE_SHIFT 4
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#define CS4234_MCLK_RATE_MASK 0x0E
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#define CS4234_MCLK_RATE_SHIFT 1
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#define CS4234_SAMPLE_WIDTH 0x07
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#define CS4234_SDOUTX_SW_MASK 0xC0
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#define CS4234_SDOUTX_SW_SHIFT 6
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#define CS4234_INPUT_SW_MASK 0x30
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#define CS4234_INPUT_SW_SHIFT 4
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#define CS4234_LOW_LAT_SW_MASK 0x0C
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#define CS4234_LOW_LAT_SW_SHIFT 2
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#define CS4234_DAC5_SW_MASK 0x03
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#define CS4234_DAC5_SW_SHIFT 0
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#define CS4234_SP_CTRL 0x08
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#define CS4234_INVT_SCLK_MASK 0x80
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#define CS4234_INVT_SCLK_SHIFT 7
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#define CS4234_DAC5_SRC_MASK 0x70
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#define CS4234_DAC5_SRC_SHIFT 4
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#define CS4234_SP_FORMAT_MASK 0x0C
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#define CS4234_SP_FORMAT_SHIFT 2
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#define CS4234_SDO_CHAIN_MASK 0x02
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#define CS4234_SDO_CHAIN_SHIFT 1
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#define CS4234_MST_SLV_MASK 0x01
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#define CS4234_MST_SLV_SHIFT 0
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#define CS4234_SP_DATA_SEL 0x09
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#define CS4234_DAC14_SRC_MASK 0x38
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#define CS4234_DAC14_SRC_SHIFT 3
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#define CS4234_LL_SRC_MASK 0x07
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#define CS4234_LL_SRC_SHIFT 0
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#define CS4234_SDIN1_MASK1 0x0A
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#define CS4234_SDIN1_MASK2 0x0B
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#define CS4234_SDIN2_MASK1 0x0C
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#define CS4234_SDIN2_MASK2 0x0D
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#define CS4234_TPS_CTRL 0x0E
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#define CS4234_TPS_MODE_MASK 0x80
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#define CS4234_TPS_MODE_SHIFT 7
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#define CS4234_TPS_OFST_MASK 0x70
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#define CS4234_TPS_OFST_SHIFT 4
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#define CS4234_GRP_DELAY_MASK 0x0F
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#define CS4234_GRP_DELAY_SHIFT 0
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#define CS4234_ADC_CTRL1 0x0F
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#define CS4234_VA_SEL_MASK 0x20
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#define CS4234_VA_SEL_SHIFT 5
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#define CS4234_ENA_HPF_MASK 0x10
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#define CS4234_ENA_HPF_SHIFT 4
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#define CS4234_INV_ADC_MASK 0x0F
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#define CS4234_INV_ADC4_MASK 0x08
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#define CS4234_INV_ADC4_SHIFT 3
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#define CS4234_INV_ADC3_MASK 0x04
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#define CS4234_INV_ADC3_SHIFT 2
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#define CS4234_INV_ADC2_MASK 0x02
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#define CS4234_INV_ADC2_SHIFT 1
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#define CS4234_INV_ADC1_MASK 0x01
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#define CS4234_INV_ADC1_SHIFT 0
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#define CS4234_ADC_CTRL2 0x10
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#define CS4234_MUTE_ADC4_MASK 0x80
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#define CS4234_MUTE_ADC4_SHIFT 7
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#define CS4234_MUTE_ADC3_MASK 0x40
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#define CS4234_MUTE_ADC3_SHIFT 6
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#define CS4234_MUTE_ADC2_MASK 0x20
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#define CS4234_MUTE_ADC2_SHIFT 5
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#define CS4234_MUTE_ADC1_MASK 0x10
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#define CS4234_MUTE_ADC1_SHIFT 4
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#define CS4234_PDN_ADC4_MASK 0x08
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#define CS4234_PDN_ADC4_SHIFT 3
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#define CS4234_PDN_ADC3_MASK 0x04
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#define CS4234_PDN_ADC3_SHIFT 2
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#define CS4234_PDN_ADC2_MASK 0x02
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#define CS4234_PDN_ADC2_SHIFT 1
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#define CS4234_PDN_ADC1_MASK 0x01
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#define CS4234_PDN_ADC1_SHIFT 0
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#define CS4234_LOW_LAT_CTRL1 0x11
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#define CS4234_LL_NG_MASK 0xE0
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#define CS4234_LL_NG_SHIFT 5
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#define CS4234_INV_LL_MASK 0x0F
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#define CS4234_INV_LL4_MASK 0x08
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#define CS4234_INV_LL4_SHIFT 3
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#define CS4234_INV_LL3_MASK 0x04
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#define CS4234_INV_LL3_SHIFT 2
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#define CS4234_INV_LL2_MASK 0x02
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#define CS4234_INV_LL2_SHIFT 1
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#define CS4234_INV_LL1_MASK 0x01
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#define CS4234_INV_LL1_SHIFT 0
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#define CS4234_DAC_CTRL1 0x12
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#define CS4234_DAC14_NG_MASK 0xE0
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#define CS4234_DAC14_NG_SHIFT 5
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#define CS4234_DAC14_DE_MASK 0x10
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#define CS4234_DAC14_DE_SHIFT 4
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#define CS4234_DAC5_DE_MASK 0x08
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#define CS4234_DAC5_DE_SHIFT 3
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#define CS4234_DAC5_MVC_MASK 0x04
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#define CS4234_DAC5_MVC_SHIFT 2
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#define CS4234_DAC5_CFG_FLTR_MASK 0x03
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#define CS4234_DAC5_CFG_FLTR_SHIFT 0
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#define CS4234_DAC_CTRL2 0x13
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#define CS4234_DAC5_NG_MASK 0xE0
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#define CS4234_DAC5_NG_SHIFT 5
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#define CS4234_INV_DAC_MASK 0x1F
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#define CS4234_INV_DAC5_MASK 0x10
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#define CS4234_INV_DAC5_SHIFT 4
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#define CS4234_INV_DAC4_MASK 0x08
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#define CS4234_INV_DAC4_SHIFT 3
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#define CS4234_INV_DAC3_MASK 0x04
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#define CS4234_INV_DAC3_SHIFT 2
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#define CS4234_INV_DAC2_MASK 0x02
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#define CS4234_INV_DAC2_SHIFT 1
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#define CS4234_INV_DAC1_MASK 0x01
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#define CS4234_INV_DAC1_SHIFT 0
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#define CS4234_DAC_CTRL3 0x14
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#define CS4234_DAC5_ATT_MASK 0x80
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#define CS4234_DAC5_ATT_SHIFT 7
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#define CS4234_DAC14_ATT_MASK 0x40
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#define CS4234_DAC14_ATT_SHIFT 6
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#define CS4234_MUTE_LL_MASK 0x20
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#define CS4234_MUTE_LL_SHIFT 5
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#define CS4234_MUTE_DAC5_MASK 0x10
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#define CS4234_MUTE_DAC5_SHIFT 4
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#define CS4234_MUTE_DAC4_MASK 0x08
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#define CS4234_MUTE_DAC4_SHIFT 3
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#define CS4234_MUTE_DAC3_MASK 0x04
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#define CS4234_MUTE_DAC3_SHIFT 2
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#define CS4234_MUTE_DAC2_MASK 0x02
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#define CS4234_MUTE_DAC2_SHIFT 1
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#define CS4234_MUTE_DAC1_MASK 0x01
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#define CS4234_MUTE_DAC1_SHIFT 0
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#define CS4234_DAC_CTRL4 0x15
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#define CS4234_VQ_RAMP_MASK 0x80
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#define CS4234_VQ_RAMP_SHIFT 7
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#define CS4234_TPS_GAIN_MASK 0x40
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#define CS4234_TPS_GAIN_SHIFT 6
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#define CS4234_PDN_DAC5_MASK 0x10
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#define CS4234_PDN_DAC5_SHIFT 4
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#define CS4234_PDN_DAC4_MASK 0x08
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#define CS4234_PDN_DAC4_SHIFT 3
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#define CS4234_PDN_DAC3_MASK 0x04
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#define CS4234_PDN_DAC3_SHIFT 2
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#define CS4234_PDN_DAC2_MASK 0x02
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#define CS4234_PDN_DAC2_SHIFT 1
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#define CS4234_PDN_DAC1_MASK 0x01
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#define CS4234_PDN_DAC1_SHIFT 0
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#define CS4234_VOLUME_MODE 0x16
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#define CS4234_MUTE_DELAY_MASK 0xC0
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#define CS4234_MUTE_DELAY_SHIFT 6
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#define CS4234_MIN_DELAY_MASK 0x38
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#define CS4234_MIN_DELAY_SHIFT 3
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#define CS4234_MAX_DELAY_MASK 0x07
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#define CS4234_MAX_DELAY_SHIFT 0
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#define CS4234_MASTER_VOL 0x17
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#define CS4234_DAC1_VOL 0x18
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#define CS4234_DAC2_VOL 0x19
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#define CS4234_DAC3_VOL 0x1A
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#define CS4234_DAC4_VOL 0x1B
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#define CS4234_DAC5_VOL 0x1C
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#define CS4234_INT_CTRL 0x1E
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#define CS4234_INT_MODE_MASK 0x80
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#define CS4234_INT_MODE_SHIFT 7
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#define CS4234_INT_PIN_MASK 0x60
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#define CS4234_INT_PIN_SHIFT 5
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#define CS4234_INT_MASK1 0x1F
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#define CS4234_MSK_TST_MODE_MASK 0x80
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#define CS4234_MSK_TST_MODE_ERR_SHIFT 7
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#define CS4234_MSK_SP_ERR_MASK 0x40
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#define CS4234_MSK_SP_ERR_SHIFT 6
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#define CS4234_MSK_CLK_ERR_MASK 0x08
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#define CS4234_MSK_CLK_ERR_SHIFT 5
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#define CS4234_MSK_ADC4_OVFL_MASK 0x08
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#define CS4234_MSK_ADC4_OVFL_SHIFT 3
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#define CS4234_MSK_ADC3_OVFL_MASK 0x04
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#define CS4234_MSK_ADC3_OVFL_SHIFT 2
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#define CS4234_MSK_ADC2_OVFL_MASK 0x02
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#define CS4234_MSK_ADC2_OVFL_SHIFT 1
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#define CS4234_MSK_ADC1_OVFL_MASK 0x01
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#define CS4234_MSK_ADC1_OVFL_SHIFT 0
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#define CS4234_INT_MASK2 0x20
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#define CS4234_MSK_DAC5_CLIP_MASK 0x10
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#define CS4234_MSK_DAC5_CLIP_SHIFT 4
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#define CS4234_MSK_DAC4_CLIP_MASK 0x08
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#define CS4234_MSK_DAC4_CLIP_SHIFT 3
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#define CS4234_MSK_DAC3_CLIP_MASK 0x04
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#define CS4234_MSK_DAC3_CLIP_SHIFT 2
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#define CS4234_MSK_DAC2_CLIP_MASK 0x02
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#define CS4234_MSK_DAC2_CLIP_SHIFT 1
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#define CS4234_MSK_DAC1_CLIP_MASK 0x01
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#define CS4234_MSK_DAC1_CLIP_SHIFT 0
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#define CS4234_INT_NOTIFY1 0x21
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#define CS4234_TST_MODE_MASK 0x80
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#define CS4234_TST_MODE_SHIFT 7
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#define CS4234_SP_ERR_MASK 0x40
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#define CS4234_SP_ERR_SHIFT 6
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#define CS4234_CLK_MOD_ERR_MASK 0x08
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#define CS4234_CLK_MOD_ERR_SHIFT 5
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#define CS4234_ADC4_OVFL_MASK 0x08
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#define CS4234_ADC4_OVFL_SHIFT 3
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#define CS4234_ADC3_OVFL_MASK 0x04
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#define CS4234_ADC3_OVFL_SHIFT 2
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#define CS4234_ADC2_OVFL_MASK 0x02
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#define CS4234_ADC2_OVFL_SHIFT 1
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#define CS4234_ADC1_OVFL_MASK 0x01
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#define CS4234_ADC1_OVFL_SHIFT 0
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#define CS4234_INT_NOTIFY2 0x22
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#define CS4234_DAC5_CLIP_MASK 0x10
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#define CS4234_DAC5_CLIP_SHIFT 4
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#define CS4234_DAC4_CLIP_MASK 0x08
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#define CS4234_DAC4_CLIP_SHIFT 3
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#define CS4234_DAC3_CLIP_MASK 0x04
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#define CS4234_DAC3_CLIP_SHIFT 2
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#define CS4234_DAC2_CLIP_MASK 0x02
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#define CS4234_DAC2_CLIP_SHIFT 1
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#define CS4234_DAC1_CLIP_MASK 0x01
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#define CS4234_DAC1_CLIP_SHIFT 0
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#define CS4234_MAX_REGISTER CS4234_INT_NOTIFY2
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#define CS4234_SUPPORTED_ID 0x423400
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#define CS4234_BOOT_TIME_US 3000
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#define CS4234_HOLD_RESET_TIME_US 1000
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#define CS4234_VQ_CHARGE_MS 1000
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#define CS4234_PCM_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
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SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
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#define CS4234_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
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SNDRV_PCM_FMTBIT_S20_LE | SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S24_3LE)
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enum cs4234_supplies {
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CS4234_SUPPLY_VA = 0,
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CS4234_SUPPLY_VL,
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};
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enum cs4234_va_sel {
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CS4234_3V3 = 0,
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CS4234_5V,
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};
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enum cs4234_sp_format {
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CS4234_LEFT_J = 0,
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CS4234_I2S,
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CS4234_TDM,
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};
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enum cs4234_base_rate_advisory {
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CS4234_48K = 0,
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CS4234_44K1,
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CS4234_32K,
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};
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#endif
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