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4d67dc1998
The max98927 codec on some devices requires pulling a reset gpio before responding to any i2c command. This commit adds support for it through an optional reset-gpios property. Signed-off-by: Alejandro Tafalla <atafalla@dnyon.com> Link: https://lore.kernel.org/r/d74b12a79ae9ca728d5d9e64c55b3e59e8c0e509.1633572679.git.atafalla@dnyon.com Signed-off-by: Mark Brown <broonie@kernel.org>
271 lines
10 KiB
C
271 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* max98927.h -- MAX98927 ALSA Soc Audio driver
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*
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* Copyright (C) 2016-2017 Maxim Integrated Products
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* Author: Ryan Lee <ryans.lee@maximintegrated.com>
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*/
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#ifndef _MAX98927_H
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#define _MAX98927_H
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/* Register Values */
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#define MAX98927_R0001_INT_RAW1 0x0001
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#define MAX98927_R0002_INT_RAW2 0x0002
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#define MAX98927_R0003_INT_RAW3 0x0003
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#define MAX98927_R0004_INT_STATE1 0x0004
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#define MAX98927_R0005_INT_STATE2 0x0005
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#define MAX98927_R0006_INT_STATE3 0x0006
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#define MAX98927_R0007_INT_FLAG1 0x0007
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#define MAX98927_R0008_INT_FLAG2 0x0008
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#define MAX98927_R0009_INT_FLAG3 0x0009
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#define MAX98927_R000A_INT_EN1 0x000A
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#define MAX98927_R000B_INT_EN2 0x000B
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#define MAX98927_R000C_INT_EN3 0x000C
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#define MAX98927_R000D_INT_FLAG_CLR1 0x000D
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#define MAX98927_R000E_INT_FLAG_CLR2 0x000E
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#define MAX98927_R000F_INT_FLAG_CLR3 0x000F
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#define MAX98927_R0010_IRQ_CTRL 0x0010
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#define MAX98927_R0011_CLK_MON 0x0011
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#define MAX98927_R0012_WDOG_CTRL 0x0012
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#define MAX98927_R0013_WDOG_RST 0x0013
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#define MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH 0x0014
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#define MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH 0x0015
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#define MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS 0x0016
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#define MAX98927_R0017_PIN_CFG 0x0017
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#define MAX98927_R0018_PCM_RX_EN_A 0x0018
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#define MAX98927_R0019_PCM_RX_EN_B 0x0019
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#define MAX98927_R001A_PCM_TX_EN_A 0x001A
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#define MAX98927_R001B_PCM_TX_EN_B 0x001B
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#define MAX98927_R001C_PCM_TX_HIZ_CTRL_A 0x001C
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#define MAX98927_R001D_PCM_TX_HIZ_CTRL_B 0x001D
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#define MAX98927_R001E_PCM_TX_CH_SRC_A 0x001E
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#define MAX98927_R001F_PCM_TX_CH_SRC_B 0x001F
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#define MAX98927_R0020_PCM_MODE_CFG 0x0020
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#define MAX98927_R0021_PCM_MASTER_MODE 0x0021
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#define MAX98927_R0022_PCM_CLK_SETUP 0x0022
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#define MAX98927_R0023_PCM_SR_SETUP1 0x0023
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#define MAX98927_R0024_PCM_SR_SETUP2 0x0024
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#define MAX98927_R0025_PCM_TO_SPK_MONOMIX_A 0x0025
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#define MAX98927_R0026_PCM_TO_SPK_MONOMIX_B 0x0026
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#define MAX98927_R0027_ICC_RX_EN_A 0x0027
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#define MAX98927_R0028_ICC_RX_EN_B 0x0028
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#define MAX98927_R002B_ICC_TX_EN_A 0x002B
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#define MAX98927_R002C_ICC_TX_EN_B 0x002C
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#define MAX98927_R002E_ICC_HIZ_MANUAL_MODE 0x002E
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#define MAX98927_R002F_ICC_TX_HIZ_EN_A 0x002F
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#define MAX98927_R0030_ICC_TX_HIZ_EN_B 0x0030
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#define MAX98927_R0031_ICC_LNK_EN 0x0031
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#define MAX98927_R0032_PDM_TX_EN 0x0032
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#define MAX98927_R0033_PDM_TX_HIZ_CTRL 0x0033
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#define MAX98927_R0034_PDM_TX_CTRL 0x0034
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#define MAX98927_R0035_PDM_RX_CTRL 0x0035
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#define MAX98927_R0036_AMP_VOL_CTRL 0x0036
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#define MAX98927_R0037_AMP_DSP_CFG 0x0037
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#define MAX98927_R0038_TONE_GEN_DC_CFG 0x0038
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#define MAX98927_R0039_DRE_CTRL 0x0039
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#define MAX98927_R003A_AMP_EN 0x003A
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#define MAX98927_R003B_SPK_SRC_SEL 0x003B
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#define MAX98927_R003C_SPK_GAIN 0x003C
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#define MAX98927_R003D_SSM_CFG 0x003D
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#define MAX98927_R003E_MEAS_EN 0x003E
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#define MAX98927_R003F_MEAS_DSP_CFG 0x003F
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#define MAX98927_R0040_BOOST_CTRL0 0x0040
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#define MAX98927_R0041_BOOST_CTRL3 0x0041
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#define MAX98927_R0042_BOOST_CTRL1 0x0042
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#define MAX98927_R0043_MEAS_ADC_CFG 0x0043
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#define MAX98927_R0044_MEAS_ADC_BASE_MSB 0x0044
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#define MAX98927_R0045_MEAS_ADC_BASE_LSB 0x0045
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#define MAX98927_R0046_ADC_CH0_DIVIDE 0x0046
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#define MAX98927_R0047_ADC_CH1_DIVIDE 0x0047
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#define MAX98927_R0048_ADC_CH2_DIVIDE 0x0048
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#define MAX98927_R0049_ADC_CH0_FILT_CFG 0x0049
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#define MAX98927_R004A_ADC_CH1_FILT_CFG 0x004A
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#define MAX98927_R004B_ADC_CH2_FILT_CFG 0x004B
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#define MAX98927_R004C_MEAS_ADC_CH0_READ 0x004C
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#define MAX98927_R004D_MEAS_ADC_CH1_READ 0x004D
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#define MAX98927_R004E_MEAS_ADC_CH2_READ 0x004E
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#define MAX98927_R0051_BROWNOUT_STATUS 0x0051
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#define MAX98927_R0052_BROWNOUT_EN 0x0052
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#define MAX98927_R0053_BROWNOUT_INFINITE_HOLD 0x0053
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#define MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR 0x0054
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#define MAX98927_R0055_BROWNOUT_LVL_HOLD 0x0055
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#define MAX98927_R005A_BROWNOUT_LVL1_THRESH 0x005A
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#define MAX98927_R005B_BROWNOUT_LVL2_THRESH 0x005B
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#define MAX98927_R005C_BROWNOUT_LVL3_THRESH 0x005C
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#define MAX98927_R005D_BROWNOUT_LVL4_THRESH 0x005D
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#define MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS 0x005E
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#define MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL 0x005F
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#define MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL 0x0060
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#define MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE 0x0061
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#define MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT 0x0072
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#define MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1 0x0073
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#define MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2 0x0074
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#define MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3 0x0075
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#define MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT 0x0076
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#define MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1 0x0077
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#define MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2 0x0078
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#define MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3 0x0079
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#define MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT 0x007A
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#define MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1 0x007B
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#define MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2 0x007C
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#define MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3 0x007D
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#define MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT 0x007E
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#define MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1 0x007F
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#define MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2 0x0080
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#define MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3 0x0081
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#define MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM 0x0082
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#define MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY 0x0083
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#define MAX98927_R0084_ENV_TRACK_REL_RATE 0x0084
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#define MAX98927_R0085_ENV_TRACK_HOLD_RATE 0x0085
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#define MAX98927_R0086_ENV_TRACK_CTRL 0x0086
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#define MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ 0x0087
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#define MAX98927_R00FF_GLOBAL_SHDN 0x00FF
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#define MAX98927_R0100_SOFT_RESET 0x0100
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#define MAX98927_R01FF_REV_ID 0x01FF
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/* MAX98927_R0018_PCM_RX_EN_A */
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#define MAX98927_PCM_RX_CH0_EN (0x1 << 0)
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#define MAX98927_PCM_RX_CH1_EN (0x1 << 1)
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#define MAX98927_PCM_RX_CH2_EN (0x1 << 2)
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#define MAX98927_PCM_RX_CH3_EN (0x1 << 3)
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#define MAX98927_PCM_RX_CH4_EN (0x1 << 4)
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#define MAX98927_PCM_RX_CH5_EN (0x1 << 5)
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#define MAX98927_PCM_RX_CH6_EN (0x1 << 6)
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#define MAX98927_PCM_RX_CH7_EN (0x1 << 7)
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/* MAX98927_R001A_PCM_TX_EN_A */
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#define MAX98927_PCM_TX_CH0_EN (0x1 << 0)
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#define MAX98927_PCM_TX_CH1_EN (0x1 << 1)
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#define MAX98927_PCM_TX_CH2_EN (0x1 << 2)
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#define MAX98927_PCM_TX_CH3_EN (0x1 << 3)
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#define MAX98927_PCM_TX_CH4_EN (0x1 << 4)
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#define MAX98927_PCM_TX_CH5_EN (0x1 << 5)
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#define MAX98927_PCM_TX_CH6_EN (0x1 << 6)
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#define MAX98927_PCM_TX_CH7_EN (0x1 << 7)
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/* MAX98927_R001E_PCM_TX_CH_SRC_A */
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#define MAX98927_PCM_TX_CH_SRC_A_V_SHIFT (0)
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#define MAX98927_PCM_TX_CH_SRC_A_I_SHIFT (4)
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/* MAX98927_R001F_PCM_TX_CH_SRC_B */
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#define MAX98927_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 5)
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/* MAX98927_R0020_PCM_MODE_CFG */
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#define MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 2)
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#define MAX98927_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
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#define MAX98927_PCM_MODE_CFG_FORMAT_SHIFT (3)
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#define MAX98927_PCM_FORMAT_I2S (0x0 << 0)
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#define MAX98927_PCM_FORMAT_LJ (0x1 << 0)
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#define MAX98927_PCM_FORMAT_TDM_MODE0 (0x3 << 0)
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#define MAX98927_PCM_FORMAT_TDM_MODE1 (0x4 << 0)
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#define MAX98927_PCM_FORMAT_TDM_MODE2 (0x5 << 0)
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#define MAX98927_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
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#define MAX98927_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
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#define MAX98927_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
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#define MAX98927_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
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/* MAX98927_R0021_PCM_MASTER_MODE */
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#define MAX98927_PCM_MASTER_MODE_MASK (0x3 << 0)
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#define MAX98927_PCM_MASTER_MODE_SLAVE (0x0 << 0)
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#define MAX98927_PCM_MASTER_MODE_MASTER (0x3 << 0)
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#define MAX98927_PCM_MASTER_MODE_MCLK_MASK (0xF << 2)
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#define MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT (2)
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/* MAX98927_R0022_PCM_CLK_SETUP */
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#define MAX98927_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
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/* MAX98927_R0023_PCM_SR_SETUP1 */
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#define MAX98927_PCM_SR_SET1_SR_MASK (0xF << 0)
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#define MAX98927_PCM_SR_SET1_SR_8000 (0x0 << 0)
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#define MAX98927_PCM_SR_SET1_SR_11025 (0x1 << 0)
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#define MAX98927_PCM_SR_SET1_SR_12000 (0x2 << 0)
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#define MAX98927_PCM_SR_SET1_SR_16000 (0x3 << 0)
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#define MAX98927_PCM_SR_SET1_SR_22050 (0x4 << 0)
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#define MAX98927_PCM_SR_SET1_SR_24000 (0x5 << 0)
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#define MAX98927_PCM_SR_SET1_SR_32000 (0x6 << 0)
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#define MAX98927_PCM_SR_SET1_SR_44100 (0x7 << 0)
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#define MAX98927_PCM_SR_SET1_SR_48000 (0x8 << 0)
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/* MAX98927_R0024_PCM_SR_SETUP2 */
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#define MAX98927_PCM_SR_SET2_SR_MASK (0xF << 4)
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#define MAX98927_PCM_SR_SET2_SR_SHIFT (4)
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#define MAX98927_PCM_SR_SET2_IVADC_SR_MASK (0xf << 0)
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/* MAX98927_R0025_PCM_TO_SPK_MONOMIX_A */
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#define MAX98927_PCM_TO_SPK_MONOMIX_CFG_MASK (0x3 << 6)
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#define MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT (6)
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/* MAX98927_R0035_PDM_RX_CTRL */
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#define MAX98927_PDM_RX_EN_MASK (0x1 << 0)
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/* MAX98927_R0036_AMP_VOL_CTRL */
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#define MAX98927_AMP_VOL_SEL (0x1 << 7)
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#define MAX98927_AMP_VOL_SEL_WIDTH (1)
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#define MAX98927_AMP_VOL_SEL_SHIFT (7)
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#define MAX98927_AMP_VOL_MASK (0x7f << 0)
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#define MAX98927_AMP_VOL_WIDTH (7)
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#define MAX98927_AMP_VOL_SHIFT (0)
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/* MAX98927_R0037_AMP_DSP_CFG */
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#define MAX98927_AMP_DSP_CFG_DCBLK_EN (0x1 << 0)
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#define MAX98927_AMP_DSP_CFG_DITH_EN (0x1 << 1)
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#define MAX98927_AMP_DSP_CFG_RMP_BYPASS (0x1 << 4)
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#define MAX98927_AMP_DSP_CFG_DAC_INV (0x1 << 5)
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#define MAX98927_AMP_DSP_CFG_RMP_SHIFT (4)
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/* MAX98927_R0039_DRE_CTRL */
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#define MAX98927_DRE_CTRL_DRE_EN (0x1 << 0)
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#define MAX98927_DRE_EN_SHIFT 0x1
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/* MAX98927_R003A_AMP_EN */
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#define MAX98927_AMP_EN_MASK (0x1 << 0)
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/* MAX98927_R003B_SPK_SRC_SEL */
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#define MAX98927_SPK_SRC_MASK (0x3 << 0)
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/* MAX98927_R003C_SPK_GAIN */
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#define MAX98927_SPK_PCM_GAIN_MASK (0x7 << 0)
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#define MAX98927_SPK_PDM_GAIN_MASK (0x7 << 4)
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#define MAX98927_SPK_GAIN_WIDTH (3)
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/* MAX98927_R003E_MEAS_EN */
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#define MAX98927_MEAS_V_EN (0x1 << 0)
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#define MAX98927_MEAS_I_EN (0x1 << 1)
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/* MAX98927_R0040_BOOST_CTRL0 */
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#define MAX98927_BOOST_CTRL0_VOUT_MASK (0x1f << 0)
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#define MAX98927_BOOST_CTRL0_PVDD_MASK (0x1 << 7)
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#define MAX98927_BOOST_CTRL0_PVDD_EN_SHIFT (7)
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/* MAX98927_R0052_BROWNOUT_EN */
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#define MAX98927_BROWNOUT_BDE_EN (0x1 << 0)
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#define MAX98927_BROWNOUT_AMP_EN (0x1 << 1)
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#define MAX98927_BROWNOUT_DSP_EN (0x1 << 2)
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#define MAX98927_BROWNOUT_DSP_SHIFT (2)
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/* MAX98927_R0100_SOFT_RESET */
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#define MAX98927_SOFT_RESET (0x1 << 0)
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/* MAX98927_R00FF_GLOBAL_SHDN */
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#define MAX98927_GLOBAL_EN_MASK (0x1 << 0)
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struct max98927_priv {
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struct regmap *regmap;
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struct snd_soc_component *component;
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struct max98927_pdata *pdata;
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struct gpio_desc *reset_gpio;
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unsigned int spk_gain;
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unsigned int sysclk;
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unsigned int v_l_slot;
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unsigned int i_l_slot;
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bool interleave_mode;
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unsigned int ch_size;
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unsigned int rate;
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unsigned int iface;
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unsigned int master;
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unsigned int digital_gain;
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bool tdm_mode;
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};
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#endif
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