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The Digital MIC (DMIC) Controller is used to interface with Pulse Density Modulation (PDM) input devices. The DMIC controller implements a converter to convert PDM signals to Pulse Code Modulation (PCM) signals. From signal flow perspective, the DMIC can be viewed as a PDM receiver. This patch registers DMIC component with ASoC framework. The component driver exposes DAPM widgets, routes and kcontrols for the device. The DAI driver exposes DMIC interfaces, which can be used to connect different components in the ASoC layer. Makefile and Kconfig support is added to allow to build the driver. The DMIC devices can be enabled in the DT via "nvidia,tegra210-dmic" compatible string. This driver can be used for Tegra186 and Tegra194 chips as well. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Link: https://lore.kernel.org/r/1595134890-16470-4-git-send-email-spujar@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
82 lines
2.2 KiB
C
82 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_dmic.h - Definitions for Tegra210 DMIC driver
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*
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* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA210_DMIC_H__
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#define __TEGRA210_DMIC_H__
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/* Register offsets from DMIC BASE */
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#define TEGRA210_DMIC_TX_STATUS 0x0c
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#define TEGRA210_DMIC_TX_INT_STATUS 0x10
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#define TEGRA210_DMIC_TX_INT_MASK 0x14
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#define TEGRA210_DMIC_TX_INT_SET 0x18
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#define TEGRA210_DMIC_TX_INT_CLEAR 0x1c
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#define TEGRA210_DMIC_TX_CIF_CTRL 0x20
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#define TEGRA210_DMIC_ENABLE 0x40
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#define TEGRA210_DMIC_SOFT_RESET 0x44
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#define TEGRA210_DMIC_CG 0x48
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#define TEGRA210_DMIC_STATUS 0x4c
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#define TEGRA210_DMIC_INT_STATUS 0x50
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#define TEGRA210_DMIC_CTRL 0x64
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#define TEGRA210_DMIC_DBG_CTRL 0x70
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#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 0x88
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#define TEGRA210_DMIC_LP_FILTER_GAIN 0x8c
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#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_0 0x90
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#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_1 0x94
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#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_2 0x98
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#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_3 0x9c
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#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_4 0xa0
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#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_0 0xa4
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#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_1 0xa8
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#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_2 0xac
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#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_3 0xb0
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#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_4 0xb4
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/* Fields in TEGRA210_DMIC_CTRL */
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#define CH_SEL_SHIFT 8
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#define TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK (0x3 << CH_SEL_SHIFT)
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#define LRSEL_POL_SHIFT 4
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#define TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT)
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#define OSR_SHIFT 0
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#define TEGRA210_DMIC_CTRL_OSR_MASK (0x3 << OSR_SHIFT)
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#define DMIC_OSR_FACTOR 64
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#define DEFAULT_GAIN_Q23 0x800000
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/* Max boost gain factor used for mixer control */
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#define MAX_BOOST_GAIN 25599
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enum tegra_dmic_ch_select {
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DMIC_CH_SELECT_LEFT,
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DMIC_CH_SELECT_RIGHT,
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DMIC_CH_SELECT_STEREO,
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};
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enum tegra_dmic_osr {
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DMIC_OSR_64,
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DMIC_OSR_128,
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DMIC_OSR_256,
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};
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enum tegra_dmic_lrsel {
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DMIC_LRSEL_LEFT,
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DMIC_LRSEL_RIGHT,
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};
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struct tegra210_dmic {
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struct clk *clk_dmic;
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struct regmap *regmap;
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unsigned int mono_to_stereo;
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unsigned int stereo_to_mono;
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unsigned int boost_gain;
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unsigned int ch_select;
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unsigned int osr_val;
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unsigned int lrsel;
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};
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#endif
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