Andy Chiu 2e1f2c1066 net: axienet: set mdio clock according to bus-frequency ... Some FPGA platforms have 80KHz MDIO bus frequency constraint when connecting Ethernet to its on-board external Marvell PHY. Thus, we may have to set MDIO clock according to the DT. Otherwise, use the default 2.5 MHz, as specified by 802.3, if the entry is not present. Also, change MAX_MDIO_FREQ to DEFAULT_MDIO_FREQ because we may actually set MDIO bus frequency higher than 2.5MHz if undelying devices support it. And properly disable the mdio bus clock in error path. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>		2022-11-21 10:36:03 +00:00
..
Kconfig	net: ethernet: xilinx: cleanup comments	2022-02-18 11:11:10 +00:00
ll_temac.h	net: ll_temac: fix the format of block comments	2022-09-21 18:25:18 -07:00
ll_temac_main.c	net: ll_temac: axienet: delete unnecessary blank lines and spaces	2022-09-21 18:25:20 -07:00
ll_temac_mdio.c	net: ll_temac: fix the format of block comments	2022-09-21 18:25:18 -07:00
Makefile
xilinx_axienet.h	net: axienet: Unexport and remove unused mdio functions	2022-11-21 10:36:03 +00:00
xilinx_axienet_main.c	net: remove explicit phylink_generic_validate() references	2022-11-07 17:54:57 -08:00
xilinx_axienet_mdio.c	net: axienet: set mdio clock according to bus-frequency	2022-11-21 10:36:03 +00:00
xilinx_emaclite.c	net: emaclite: update reset_lock member documentation	2022-10-28 11:39:57 +01:00