mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 22:02:02 +00:00
65f5dd4f02
Cross-merge networking fixes after downstream PR. Conflicts: net/mptcp/protocol.cadf1bb78da
("mptcp: fix snd_wnd initialization for passive socket")9426ce476a
("mptcp: annotate lockless access for RX path fields") https://lore.kernel.org/all/20240228103048.19255709@canb.auug.org.au/ Adjacent changes: drivers/dpll/dpll_core.c0d60d8df6f
("dpll: rely on rcu for netdev_dpll_pin()")e7f8df0e81
("dpll: move xa_erase() call in to match dpll_pin_alloc() error path order") drivers/net/veth.c1ce7d306ea
("veth: try harder when allocating queue memory")0bef512012
("net: add netdev_lockdep_set_classes() to virtual drivers") drivers/net/wireless/intel/iwlwifi/mvm/d3.c8c9bef26e9
("wifi: iwlwifi: mvm: d3: implement suspend with MLO")78f65fbf42
("wifi: iwlwifi: mvm: ensure offloading TID queue exists") net/wireless/nl80211.cf78c137533
("wifi: nl80211: reject iftype change with mesh ID change")414532d8aa
("wifi: cfg80211: use IEEE80211_MAX_MESH_ID_LEN appropriately") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
182 lines
6 KiB
C
182 lines
6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Meta Platforms, Inc. and affiliates
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* Copyright (c) 2023 Intel and affiliates
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*/
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#ifndef __DPLL_H__
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#define __DPLL_H__
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#include <uapi/linux/dpll.h>
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#include <linux/device.h>
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#include <linux/netlink.h>
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#include <linux/netdevice.h>
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#include <linux/rtnetlink.h>
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struct dpll_device;
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struct dpll_pin;
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struct dpll_device_ops {
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int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
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enum dpll_mode *mode, struct netlink_ext_ack *extack);
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int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
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enum dpll_lock_status *status,
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enum dpll_lock_status_error *status_error,
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struct netlink_ext_ack *extack);
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int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
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s32 *temp, struct netlink_ext_ack *extack);
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};
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struct dpll_pin_ops {
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int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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const u64 frequency,
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struct netlink_ext_ack *extack);
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int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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u64 *frequency, struct netlink_ext_ack *extack);
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int (*direction_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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const enum dpll_pin_direction direction,
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struct netlink_ext_ack *extack);
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int (*direction_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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enum dpll_pin_direction *direction,
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struct netlink_ext_ack *extack);
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int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_pin *parent_pin,
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void *parent_pin_priv,
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enum dpll_pin_state *state,
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struct netlink_ext_ack *extack);
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int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll,
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void *dpll_priv, enum dpll_pin_state *state,
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struct netlink_ext_ack *extack);
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int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_pin *parent_pin,
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void *parent_pin_priv,
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const enum dpll_pin_state state,
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struct netlink_ext_ack *extack);
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int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll,
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void *dpll_priv,
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const enum dpll_pin_state state,
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struct netlink_ext_ack *extack);
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int (*prio_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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u32 *prio, struct netlink_ext_ack *extack);
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int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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const u32 prio, struct netlink_ext_ack *extack);
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int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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s64 *phase_offset,
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struct netlink_ext_ack *extack);
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int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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s32 *phase_adjust,
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struct netlink_ext_ack *extack);
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int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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const s32 phase_adjust,
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struct netlink_ext_ack *extack);
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int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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s64 *ffo, struct netlink_ext_ack *extack);
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};
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struct dpll_pin_frequency {
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u64 min;
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u64 max;
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};
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#define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \
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{ \
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.min = _min, \
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.max = _max, \
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}
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#define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val)
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#define DPLL_PIN_FREQUENCY_1PPS \
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DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ)
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#define DPLL_PIN_FREQUENCY_10MHZ \
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DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ)
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#define DPLL_PIN_FREQUENCY_IRIG_B \
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DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ)
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#define DPLL_PIN_FREQUENCY_DCF77 \
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DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
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struct dpll_pin_phase_adjust_range {
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s32 min;
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s32 max;
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};
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struct dpll_pin_properties {
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const char *board_label;
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const char *panel_label;
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const char *package_label;
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enum dpll_pin_type type;
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unsigned long capabilities;
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u32 freq_supported_num;
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struct dpll_pin_frequency *freq_supported;
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struct dpll_pin_phase_adjust_range phase_range;
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};
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#if IS_ENABLED(CONFIG_DPLL)
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size_t dpll_msg_pin_handle_size(struct dpll_pin *pin);
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int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin);
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#else
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static inline size_t dpll_msg_pin_handle_size(struct dpll_pin *pin)
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{
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return 0;
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}
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static inline int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin)
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{
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return 0;
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}
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#endif
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struct dpll_device *
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dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module);
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void dpll_device_put(struct dpll_device *dpll);
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int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,
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const struct dpll_device_ops *ops, void *priv);
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void dpll_device_unregister(struct dpll_device *dpll,
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const struct dpll_device_ops *ops, void *priv);
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struct dpll_pin *
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dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module,
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const struct dpll_pin_properties *prop);
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int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
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const struct dpll_pin_ops *ops, void *priv);
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void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,
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const struct dpll_pin_ops *ops, void *priv);
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void dpll_pin_put(struct dpll_pin *pin);
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int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin,
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const struct dpll_pin_ops *ops, void *priv);
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void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin,
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const struct dpll_pin_ops *ops, void *priv);
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int dpll_device_change_ntf(struct dpll_device *dpll);
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int dpll_pin_change_ntf(struct dpll_pin *pin);
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#if !IS_ENABLED(CONFIG_DPLL)
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static inline struct dpll_pin *netdev_dpll_pin(const struct net_device *dev)
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{
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return NULL;
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}
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#else
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struct dpll_pin *netdev_dpll_pin(const struct net_device *dev);
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#endif
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#endif
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