Shay Drory 3663ad34bc net/mlx5: Shift control IRQ to the last index ... Control IRQ is the first IRQ vector. This complicates handling of completion irqs as we need to offset them by one. in the next patch, there are scenarios where completion and control EQs will share the same irq. for example: functions with single IRQ. To ease such scenarios, we shift control IRQ to the end of the irq array. Signed-off-by: Shay Drory <shayd@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>		2021-10-04 18:10:57 -07:00
..
accel.h
cq.h
device.h	net/mlx5: Allocate individual capability	2021-08-11 11:14:33 -07:00
doorbell.h
driver.h	net/mlx5: Shift control IRQ to the last index	2021-10-04 18:10:57 -07:00
eq.h	net/mlx5: Provide cpumask at EQ creation phase	2021-06-14 20:57:57 -07:00
eswitch.h	net/mlx5: Bridge, mark reg_c1 when pushing VLAN	2021-10-04 18:10:56 -07:00
fs.h	net/mlx5: Move TTC logic to fs_ttc	2021-08-02 19:26:26 -07:00
fs_helpers.h
mlx5_ifc.h	net/mlx5: E-switch, Introduce rate limiting groups API	2021-08-19 21:50:40 -07:00
mlx5_ifc_fpga.h
mlx5_ifc_vdpa.h	vdpa/mlx5: Fix queue type selection logic	2021-08-11 06:44:43 -04:00
mpfs.h
port.h
qp.h	RDMA/mlx5: Refactor get_ts_format functions to simplify code	2021-06-22 09:35:16 +03:00
rsc_dump.h
transobj.h	net/mlx5e: Fix page reclaim for dead peer hairpin	2021-06-09 17:20:03 -07:00
vport.h