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![Julia Lawall](/assets/img/avatar_default.png)
Check that the result of kmalloc is not NULL before passing it to other functions. The semantic match that finds this problem is as follows: (http://www.emn.fr/x-info/coccinelle/) // <smpl> @@ expression *x; identifier f; constant char *C; @@ x = \(kmalloc\|kcalloc\|kzalloc\)(...); ... when != x == NULL when != x != NULL when != (x || ...) ( kfree(x) f(...,C,...,x,...) | *f(...,x,...) | *x->f ) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Matt Turner <mattst88@gmail.com>
798 lines
20 KiB
C
798 lines
20 KiB
C
/*
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* linux/arch/alpha/kernel/core_titan.c
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*
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* Code common to all TITAN core logic chips.
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*/
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#define __EXTERN_INLINE inline
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#include <asm/io.h>
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#include <asm/core_titan.h>
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#undef __EXTERN_INLINE
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/vmalloc.h>
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#include <linux/bootmem.h>
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#include <asm/ptrace.h>
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#include <asm/smp.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/vga.h>
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#include "proto.h"
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#include "pci_impl.h"
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/* Save Titan configuration data as the console had it set up. */
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struct
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{
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unsigned long wsba[4];
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unsigned long wsm[4];
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unsigned long tba[4];
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} saved_config[4] __attribute__((common));
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/*
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* Is PChip 1 present? No need to query it more than once.
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*/
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static int titan_pchip1_present;
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/*
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* BIOS32-style PCI interface:
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*/
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#define DEBUG_CONFIG 0
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#if DEBUG_CONFIG
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# define DBG_CFG(args) printk args
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#else
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# define DBG_CFG(args)
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#endif
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/*
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* Routines to access TIG registers.
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*/
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static inline volatile unsigned long *
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mk_tig_addr(int offset)
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{
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return (volatile unsigned long *)(TITAN_TIG_SPACE + (offset << 6));
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}
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static inline u8
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titan_read_tig(int offset, u8 value)
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{
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volatile unsigned long *tig_addr = mk_tig_addr(offset);
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return (u8)(*tig_addr & 0xff);
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}
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static inline void
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titan_write_tig(int offset, u8 value)
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{
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volatile unsigned long *tig_addr = mk_tig_addr(offset);
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*tig_addr = (unsigned long)value;
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}
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/*
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* Given a bus, device, and function number, compute resulting
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* configuration space address
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* accordingly. It is therefore not safe to have concurrent
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* invocations to configuration space access routines, but there
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* really shouldn't be any need for this.
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*
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* Note that all config space accesses use Type 1 address format.
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*
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* Note also that type 1 is determined by non-zero bus number.
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*
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* Type 1:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:24 reserved
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* 23:16 bus number (8 bits = 128 possible buses)
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* 15:11 Device number (5 bits)
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* 10:8 function number
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* 7:2 register number
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*
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* Notes:
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* The function number selects which function of a multi-function device
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* (e.g., SCSI and Ethernet).
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*
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* The register selects a DWORD (32 bit) register offset. Hence it
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* doesn't get shifted by 2 bits as we want to "drop" the bottom two
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* bits.
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*/
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static int
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mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
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unsigned long *pci_addr, unsigned char *type1)
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{
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struct pci_controller *hose = pbus->sysdata;
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unsigned long addr;
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u8 bus = pbus->number;
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DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
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"pci_addr=0x%p, type1=0x%p)\n",
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bus, device_fn, where, pci_addr, type1));
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if (!pbus->parent) /* No parent means peer PCI bus. */
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bus = 0;
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*type1 = (bus != 0);
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addr = (bus << 16) | (device_fn << 8) | where;
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addr |= hose->config_space_base;
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*pci_addr = addr;
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DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
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return 0;
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}
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static int
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titan_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr;
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unsigned char type1;
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if (mk_conf_addr(bus, devfn, where, &addr, &type1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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*value = __kernel_ldbu(*(vucp)addr);
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break;
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case 2:
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*value = __kernel_ldwu(*(vusp)addr);
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break;
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case 4:
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*value = *(vuip)addr;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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titan_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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unsigned long addr;
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unsigned char type1;
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if (mk_conf_addr(bus, devfn, where, &addr, &type1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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__kernel_stb(value, *(vucp)addr);
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mb();
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__kernel_ldbu(*(vucp)addr);
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break;
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case 2:
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__kernel_stw(value, *(vusp)addr);
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mb();
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__kernel_ldwu(*(vusp)addr);
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break;
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case 4:
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*(vuip)addr = value;
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mb();
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*(vuip)addr;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops titan_pci_ops =
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{
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.read = titan_read_config,
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.write = titan_write_config,
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};
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void
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titan_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
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{
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titan_pachip *pachip =
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(hose->index & 1) ? TITAN_pachip1 : TITAN_pachip0;
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titan_pachip_port *port;
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volatile unsigned long *csr;
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unsigned long value;
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/* Get the right hose. */
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port = &pachip->g_port;
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if (hose->index & 2)
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port = &pachip->a_port;
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/* We can invalidate up to 8 tlb entries in a go. The flush
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matches against <31:16> in the pci address.
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Note that gtlbi* and atlbi* are in the same place in the g_port
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and a_port, respectively, so the g_port offset can be used
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even if hose is an a_port */
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csr = &port->port_specific.g.gtlbia.csr;
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if (((start ^ end) & 0xffff0000) == 0)
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csr = &port->port_specific.g.gtlbiv.csr;
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/* For TBIA, it doesn't matter what value we write. For TBI,
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it's the shifted tag bits. */
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value = (start & 0xffff0000) >> 12;
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wmb();
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*csr = value;
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mb();
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*csr;
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}
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static int
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titan_query_agp(titan_pachip_port *port)
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{
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union TPAchipPCTL pctl;
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/* set up APCTL */
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pctl.pctl_q_whole = port->pctl.csr;
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return pctl.pctl_r_bits.apctl_v_agp_present;
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}
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static void __init
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titan_init_one_pachip_port(titan_pachip_port *port, int index)
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{
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struct pci_controller *hose;
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hose = alloc_pci_controller();
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if (index == 0)
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pci_isa_hose = hose;
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hose->io_space = alloc_resource();
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hose->mem_space = alloc_resource();
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/*
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* This is for userland consumption. The 40-bit PIO bias that we
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* use in the kernel through KSEG doesn't work in the page table
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* based user mappings. (43-bit KSEG sign extends the physical
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* address from bit 40 to hit the I/O bit - mapped addresses don't).
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* So make sure we get the 43-bit PIO bias.
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*/
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hose->sparse_mem_base = 0;
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hose->sparse_io_base = 0;
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hose->dense_mem_base
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= (TITAN_MEM(index) & 0xffffffffffUL) | 0x80000000000UL;
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hose->dense_io_base
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= (TITAN_IO(index) & 0xffffffffffUL) | 0x80000000000UL;
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hose->config_space_base = TITAN_CONF(index);
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hose->index = index;
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hose->io_space->start = TITAN_IO(index) - TITAN_IO_BIAS;
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hose->io_space->end = hose->io_space->start + TITAN_IO_SPACE - 1;
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hose->io_space->name = pci_io_names[index];
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hose->io_space->flags = IORESOURCE_IO;
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hose->mem_space->start = TITAN_MEM(index) - TITAN_MEM_BIAS;
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hose->mem_space->end = hose->mem_space->start + 0xffffffff;
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hose->mem_space->name = pci_mem_names[index];
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hose->mem_space->flags = IORESOURCE_MEM;
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if (request_resource(&ioport_resource, hose->io_space) < 0)
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printk(KERN_ERR "Failed to request IO on hose %d\n", index);
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if (request_resource(&iomem_resource, hose->mem_space) < 0)
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printk(KERN_ERR "Failed to request MEM on hose %d\n", index);
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/*
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* Save the existing PCI window translations. SRM will
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* need them when we go to reboot.
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*/
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saved_config[index].wsba[0] = port->wsba[0].csr;
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saved_config[index].wsm[0] = port->wsm[0].csr;
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saved_config[index].tba[0] = port->tba[0].csr;
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saved_config[index].wsba[1] = port->wsba[1].csr;
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saved_config[index].wsm[1] = port->wsm[1].csr;
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saved_config[index].tba[1] = port->tba[1].csr;
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saved_config[index].wsba[2] = port->wsba[2].csr;
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saved_config[index].wsm[2] = port->wsm[2].csr;
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saved_config[index].tba[2] = port->tba[2].csr;
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saved_config[index].wsba[3] = port->wsba[3].csr;
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saved_config[index].wsm[3] = port->wsm[3].csr;
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saved_config[index].tba[3] = port->tba[3].csr;
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/*
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* Set up the PCI to main memory translation windows.
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*
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* Note: Window 3 on Titan is Scatter-Gather ONLY.
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*
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* Window 0 is scatter-gather 8MB at 8MB (for isa)
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* Window 1 is direct access 1GB at 2GB
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* Window 2 is scatter-gather 1GB at 3GB
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*/
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hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
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hose->sg_isa->align_entry = 8; /* 64KB for ISA */
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hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, 0);
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hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */
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port->wsba[0].csr = hose->sg_isa->dma_base | 3;
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port->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000;
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port->tba[0].csr = virt_to_phys(hose->sg_isa->ptes);
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port->wsba[1].csr = __direct_map_base | 1;
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port->wsm[1].csr = (__direct_map_size - 1) & 0xfff00000;
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port->tba[1].csr = 0;
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port->wsba[2].csr = hose->sg_pci->dma_base | 3;
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port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000;
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port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes);
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port->wsba[3].csr = 0;
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/* Enable the Monster Window to make DAC pci64 possible. */
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port->pctl.csr |= pctl_m_mwin;
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/*
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* If it's an AGP port, initialize agplastwr.
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*/
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if (titan_query_agp(port))
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port->port_specific.a.agplastwr.csr = __direct_map_base;
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titan_pci_tbi(hose, 0, -1);
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}
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static void __init
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titan_init_pachips(titan_pachip *pachip0, titan_pachip *pachip1)
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{
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titan_pchip1_present = TITAN_cchip->csc.csr & 1L<<14;
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/* Init the ports in hose order... */
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titan_init_one_pachip_port(&pachip0->g_port, 0); /* hose 0 */
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if (titan_pchip1_present)
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titan_init_one_pachip_port(&pachip1->g_port, 1);/* hose 1 */
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titan_init_one_pachip_port(&pachip0->a_port, 2); /* hose 2 */
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if (titan_pchip1_present)
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titan_init_one_pachip_port(&pachip1->a_port, 3);/* hose 3 */
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}
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void __init
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titan_init_arch(void)
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{
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#if 0
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printk("%s: titan_init_arch()\n", __func__);
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printk("%s: CChip registers:\n", __func__);
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printk("%s: CSR_CSC 0x%lx\n", __func__, TITAN_cchip->csc.csr);
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printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr);
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printk("%s: CSR_MISC 0x%lx\n", __func__, TITAN_cchip->misc.csr);
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printk("%s: CSR_DIM0 0x%lx\n", __func__, TITAN_cchip->dim0.csr);
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printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr);
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printk("%s: CSR_DIR0 0x%lx\n", __func__, TITAN_cchip->dir0.csr);
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printk("%s: CSR_DIR1 0x%lx\n", __func__, TITAN_cchip->dir1.csr);
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printk("%s: CSR_DRIR 0x%lx\n", __func__, TITAN_cchip->drir.csr);
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printk("%s: DChip registers:\n", __func__);
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printk("%s: CSR_DSC 0x%lx\n", __func__, TITAN_dchip->dsc.csr);
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printk("%s: CSR_STR 0x%lx\n", __func__, TITAN_dchip->str.csr);
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printk("%s: CSR_DREV 0x%lx\n", __func__, TITAN_dchip->drev.csr);
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#endif
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boot_cpuid = __hard_smp_processor_id();
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/* With multiple PCI busses, we play with I/O as physical addrs. */
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ioport_resource.end = ~0UL;
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iomem_resource.end = ~0UL;
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/* PCI DMA Direct Mapping is 1GB at 2GB. */
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__direct_map_base = 0x80000000;
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__direct_map_size = 0x40000000;
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/* Init the PA chip(s). */
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titan_init_pachips(TITAN_pachip0, TITAN_pachip1);
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/* Check for graphic console location (if any). */
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find_console_vga_hose();
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}
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static void
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titan_kill_one_pachip_port(titan_pachip_port *port, int index)
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{
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port->wsba[0].csr = saved_config[index].wsba[0];
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port->wsm[0].csr = saved_config[index].wsm[0];
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port->tba[0].csr = saved_config[index].tba[0];
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port->wsba[1].csr = saved_config[index].wsba[1];
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port->wsm[1].csr = saved_config[index].wsm[1];
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port->tba[1].csr = saved_config[index].tba[1];
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port->wsba[2].csr = saved_config[index].wsba[2];
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port->wsm[2].csr = saved_config[index].wsm[2];
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port->tba[2].csr = saved_config[index].tba[2];
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port->wsba[3].csr = saved_config[index].wsba[3];
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port->wsm[3].csr = saved_config[index].wsm[3];
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port->tba[3].csr = saved_config[index].tba[3];
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}
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static void
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titan_kill_pachips(titan_pachip *pachip0, titan_pachip *pachip1)
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{
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if (titan_pchip1_present) {
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titan_kill_one_pachip_port(&pachip1->g_port, 1);
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titan_kill_one_pachip_port(&pachip1->a_port, 3);
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}
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titan_kill_one_pachip_port(&pachip0->g_port, 0);
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titan_kill_one_pachip_port(&pachip0->a_port, 2);
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}
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void
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titan_kill_arch(int mode)
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{
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titan_kill_pachips(TITAN_pachip0, TITAN_pachip1);
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}
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/*
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* IO map support.
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*/
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void __iomem *
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titan_ioportmap(unsigned long addr)
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{
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FIXUP_IOADDR_VGA(addr);
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return (void __iomem *)(addr + TITAN_IO_BIAS);
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}
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||
|
||
void __iomem *
|
||
titan_ioremap(unsigned long addr, unsigned long size)
|
||
{
|
||
int h = (addr & TITAN_HOSE_MASK) >> TITAN_HOSE_SHIFT;
|
||
unsigned long baddr = addr & ~TITAN_HOSE_MASK;
|
||
unsigned long last = baddr + size - 1;
|
||
struct pci_controller *hose;
|
||
struct vm_struct *area;
|
||
unsigned long vaddr;
|
||
unsigned long *ptes;
|
||
unsigned long pfn;
|
||
|
||
/*
|
||
* Adjust the address and hose, if necessary.
|
||
*/
|
||
if (pci_vga_hose && __is_mem_vga(addr)) {
|
||
h = pci_vga_hose->index;
|
||
addr += pci_vga_hose->mem_space->start;
|
||
}
|
||
|
||
/*
|
||
* Find the hose.
|
||
*/
|
||
for (hose = hose_head; hose; hose = hose->next)
|
||
if (hose->index == h)
|
||
break;
|
||
if (!hose)
|
||
return NULL;
|
||
|
||
/*
|
||
* Is it direct-mapped?
|
||
*/
|
||
if ((baddr >= __direct_map_base) &&
|
||
((baddr + size - 1) < __direct_map_base + __direct_map_size)) {
|
||
vaddr = addr - __direct_map_base + TITAN_MEM_BIAS;
|
||
return (void __iomem *) vaddr;
|
||
}
|
||
|
||
/*
|
||
* Check the scatter-gather arena.
|
||
*/
|
||
if (hose->sg_pci &&
|
||
baddr >= (unsigned long)hose->sg_pci->dma_base &&
|
||
last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size){
|
||
|
||
/*
|
||
* Adjust the limits (mappings must be page aligned)
|
||
*/
|
||
baddr -= hose->sg_pci->dma_base;
|
||
last -= hose->sg_pci->dma_base;
|
||
baddr &= PAGE_MASK;
|
||
size = PAGE_ALIGN(last) - baddr;
|
||
|
||
/*
|
||
* Map it
|
||
*/
|
||
area = get_vm_area(size, VM_IOREMAP);
|
||
if (!area) {
|
||
printk("ioremap failed... no vm_area...\n");
|
||
return NULL;
|
||
}
|
||
|
||
ptes = hose->sg_pci->ptes;
|
||
for (vaddr = (unsigned long)area->addr;
|
||
baddr <= last;
|
||
baddr += PAGE_SIZE, vaddr += PAGE_SIZE) {
|
||
pfn = ptes[baddr >> PAGE_SHIFT];
|
||
if (!(pfn & 1)) {
|
||
printk("ioremap failed... pte not valid...\n");
|
||
vfree(area->addr);
|
||
return NULL;
|
||
}
|
||
pfn >>= 1; /* make it a true pfn */
|
||
|
||
if (__alpha_remap_area_pages(vaddr,
|
||
pfn << PAGE_SHIFT,
|
||
PAGE_SIZE, 0)) {
|
||
printk("FAILED to remap_area_pages...\n");
|
||
vfree(area->addr);
|
||
return NULL;
|
||
}
|
||
}
|
||
|
||
flush_tlb_all();
|
||
|
||
vaddr = (unsigned long)area->addr + (addr & ~PAGE_MASK);
|
||
return (void __iomem *) vaddr;
|
||
}
|
||
|
||
/* Assume a legacy (read: VGA) address, and return appropriately. */
|
||
return (void __iomem *)(addr + TITAN_MEM_BIAS);
|
||
}
|
||
|
||
void
|
||
titan_iounmap(volatile void __iomem *xaddr)
|
||
{
|
||
unsigned long addr = (unsigned long) xaddr;
|
||
if (addr >= VMALLOC_START)
|
||
vfree((void *)(PAGE_MASK & addr));
|
||
}
|
||
|
||
int
|
||
titan_is_mmio(const volatile void __iomem *xaddr)
|
||
{
|
||
unsigned long addr = (unsigned long) xaddr;
|
||
|
||
if (addr >= VMALLOC_START)
|
||
return 1;
|
||
else
|
||
return (addr & 0x100000000UL) == 0;
|
||
}
|
||
|
||
#ifndef CONFIG_ALPHA_GENERIC
|
||
EXPORT_SYMBOL(titan_ioportmap);
|
||
EXPORT_SYMBOL(titan_ioremap);
|
||
EXPORT_SYMBOL(titan_iounmap);
|
||
EXPORT_SYMBOL(titan_is_mmio);
|
||
#endif
|
||
|
||
/*
|
||
* AGP GART Support.
|
||
*/
|
||
#include <linux/agp_backend.h>
|
||
#include <asm/agp_backend.h>
|
||
#include <linux/slab.h>
|
||
#include <linux/delay.h>
|
||
|
||
struct titan_agp_aperture {
|
||
struct pci_iommu_arena *arena;
|
||
long pg_start;
|
||
long pg_count;
|
||
};
|
||
|
||
static int
|
||
titan_agp_setup(alpha_agp_info *agp)
|
||
{
|
||
struct titan_agp_aperture *aper;
|
||
|
||
if (!alpha_agpgart_size)
|
||
return -ENOMEM;
|
||
|
||
aper = kmalloc(sizeof(struct titan_agp_aperture), GFP_KERNEL);
|
||
if (aper == NULL)
|
||
return -ENOMEM;
|
||
|
||
aper->arena = agp->hose->sg_pci;
|
||
aper->pg_count = alpha_agpgart_size / PAGE_SIZE;
|
||
aper->pg_start = iommu_reserve(aper->arena, aper->pg_count,
|
||
aper->pg_count - 1);
|
||
if (aper->pg_start < 0) {
|
||
printk(KERN_ERR "Failed to reserve AGP memory\n");
|
||
kfree(aper);
|
||
return -ENOMEM;
|
||
}
|
||
|
||
agp->aperture.bus_base =
|
||
aper->arena->dma_base + aper->pg_start * PAGE_SIZE;
|
||
agp->aperture.size = aper->pg_count * PAGE_SIZE;
|
||
agp->aperture.sysdata = aper;
|
||
|
||
return 0;
|
||
}
|
||
|
||
static void
|
||
titan_agp_cleanup(alpha_agp_info *agp)
|
||
{
|
||
struct titan_agp_aperture *aper = agp->aperture.sysdata;
|
||
int status;
|
||
|
||
status = iommu_release(aper->arena, aper->pg_start, aper->pg_count);
|
||
if (status == -EBUSY) {
|
||
printk(KERN_WARNING
|
||
"Attempted to release bound AGP memory - unbinding\n");
|
||
iommu_unbind(aper->arena, aper->pg_start, aper->pg_count);
|
||
status = iommu_release(aper->arena, aper->pg_start,
|
||
aper->pg_count);
|
||
}
|
||
if (status < 0)
|
||
printk(KERN_ERR "Failed to release AGP memory\n");
|
||
|
||
kfree(aper);
|
||
kfree(agp);
|
||
}
|
||
|
||
static int
|
||
titan_agp_configure(alpha_agp_info *agp)
|
||
{
|
||
union TPAchipPCTL pctl;
|
||
titan_pachip_port *port = agp->private;
|
||
pctl.pctl_q_whole = port->pctl.csr;
|
||
|
||
/* Side-Band Addressing? */
|
||
pctl.pctl_r_bits.apctl_v_agp_sba_en = agp->mode.bits.sba;
|
||
|
||
/* AGP Rate? */
|
||
pctl.pctl_r_bits.apctl_v_agp_rate = 0; /* 1x */
|
||
if (agp->mode.bits.rate & 2)
|
||
pctl.pctl_r_bits.apctl_v_agp_rate = 1; /* 2x */
|
||
#if 0
|
||
if (agp->mode.bits.rate & 4)
|
||
pctl.pctl_r_bits.apctl_v_agp_rate = 2; /* 4x */
|
||
#endif
|
||
|
||
/* RQ Depth? */
|
||
pctl.pctl_r_bits.apctl_v_agp_hp_rd = 2;
|
||
pctl.pctl_r_bits.apctl_v_agp_lp_rd = 7;
|
||
|
||
/*
|
||
* AGP Enable.
|
||
*/
|
||
pctl.pctl_r_bits.apctl_v_agp_en = agp->mode.bits.enable;
|
||
|
||
/* Tell the user. */
|
||
printk("Enabling AGP: %dX%s\n",
|
||
1 << pctl.pctl_r_bits.apctl_v_agp_rate,
|
||
pctl.pctl_r_bits.apctl_v_agp_sba_en ? " - SBA" : "");
|
||
|
||
/* Write it. */
|
||
port->pctl.csr = pctl.pctl_q_whole;
|
||
|
||
/* And wait at least 5000 66MHz cycles (per Titan spec). */
|
||
udelay(100);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static int
|
||
titan_agp_bind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem)
|
||
{
|
||
struct titan_agp_aperture *aper = agp->aperture.sysdata;
|
||
return iommu_bind(aper->arena, aper->pg_start + pg_start,
|
||
mem->page_count, mem->pages);
|
||
}
|
||
|
||
static int
|
||
titan_agp_unbind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem)
|
||
{
|
||
struct titan_agp_aperture *aper = agp->aperture.sysdata;
|
||
return iommu_unbind(aper->arena, aper->pg_start + pg_start,
|
||
mem->page_count);
|
||
}
|
||
|
||
static unsigned long
|
||
titan_agp_translate(alpha_agp_info *agp, dma_addr_t addr)
|
||
{
|
||
struct titan_agp_aperture *aper = agp->aperture.sysdata;
|
||
unsigned long baddr = addr - aper->arena->dma_base;
|
||
unsigned long pte;
|
||
|
||
if (addr < agp->aperture.bus_base ||
|
||
addr >= agp->aperture.bus_base + agp->aperture.size) {
|
||
printk("%s: addr out of range\n", __func__);
|
||
return -EINVAL;
|
||
}
|
||
|
||
pte = aper->arena->ptes[baddr >> PAGE_SHIFT];
|
||
if (!(pte & 1)) {
|
||
printk("%s: pte not valid\n", __func__);
|
||
return -EINVAL;
|
||
}
|
||
|
||
return (pte >> 1) << PAGE_SHIFT;
|
||
}
|
||
|
||
struct alpha_agp_ops titan_agp_ops =
|
||
{
|
||
.setup = titan_agp_setup,
|
||
.cleanup = titan_agp_cleanup,
|
||
.configure = titan_agp_configure,
|
||
.bind = titan_agp_bind_memory,
|
||
.unbind = titan_agp_unbind_memory,
|
||
.translate = titan_agp_translate
|
||
};
|
||
|
||
alpha_agp_info *
|
||
titan_agp_info(void)
|
||
{
|
||
alpha_agp_info *agp;
|
||
struct pci_controller *hose;
|
||
titan_pachip_port *port;
|
||
int hosenum = -1;
|
||
union TPAchipPCTL pctl;
|
||
|
||
/*
|
||
* Find the AGP port.
|
||
*/
|
||
port = &TITAN_pachip0->a_port;
|
||
if (titan_query_agp(port))
|
||
hosenum = 2;
|
||
if (hosenum < 0 &&
|
||
titan_pchip1_present &&
|
||
titan_query_agp(port = &TITAN_pachip1->a_port))
|
||
hosenum = 3;
|
||
|
||
/*
|
||
* Find the hose the port is on.
|
||
*/
|
||
for (hose = hose_head; hose; hose = hose->next)
|
||
if (hose->index == hosenum)
|
||
break;
|
||
|
||
if (!hose || !hose->sg_pci)
|
||
return NULL;
|
||
|
||
/*
|
||
* Allocate the info structure.
|
||
*/
|
||
agp = kmalloc(sizeof(*agp), GFP_KERNEL);
|
||
if (!agp)
|
||
return NULL;
|
||
|
||
/*
|
||
* Fill it in.
|
||
*/
|
||
agp->hose = hose;
|
||
agp->private = port;
|
||
agp->ops = &titan_agp_ops;
|
||
|
||
/*
|
||
* Aperture - not configured until ops.setup().
|
||
*
|
||
* FIXME - should we go ahead and allocate it here?
|
||
*/
|
||
agp->aperture.bus_base = 0;
|
||
agp->aperture.size = 0;
|
||
agp->aperture.sysdata = NULL;
|
||
|
||
/*
|
||
* Capabilities.
|
||
*/
|
||
agp->capability.lw = 0;
|
||
agp->capability.bits.rate = 3; /* 2x, 1x */
|
||
agp->capability.bits.sba = 1;
|
||
agp->capability.bits.rq = 7; /* 8 - 1 */
|
||
|
||
/*
|
||
* Mode.
|
||
*/
|
||
pctl.pctl_q_whole = port->pctl.csr;
|
||
agp->mode.lw = 0;
|
||
agp->mode.bits.rate = 1 << pctl.pctl_r_bits.apctl_v_agp_rate;
|
||
agp->mode.bits.sba = pctl.pctl_r_bits.apctl_v_agp_sba_en;
|
||
agp->mode.bits.rq = 7; /* RQ Depth? */
|
||
agp->mode.bits.enable = pctl.pctl_r_bits.apctl_v_agp_en;
|
||
|
||
return agp;
|
||
}
|