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![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
966 lines
25 KiB
C
966 lines
25 KiB
C
/*
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* linux/arch/alpha/kernel/pci_iommu.c
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/pci.h>
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#include <linux/gfp.h>
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#include <linux/bootmem.h>
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#include <linux/scatterlist.h>
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#include <linux/log2.h>
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#include <linux/dma-mapping.h>
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#include <linux/iommu-helper.h>
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#include <asm/io.h>
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#include <asm/hwrpb.h>
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#include "proto.h"
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#include "pci_impl.h"
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#define DEBUG_ALLOC 0
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#if DEBUG_ALLOC > 0
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# define DBGA(args...) printk(KERN_DEBUG args)
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#else
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# define DBGA(args...)
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#endif
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#if DEBUG_ALLOC > 1
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# define DBGA2(args...) printk(KERN_DEBUG args)
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#else
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# define DBGA2(args...)
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#endif
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#define DEBUG_NODIRECT 0
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#define ISA_DMA_MASK 0x00ffffff
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static inline unsigned long
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mk_iommu_pte(unsigned long paddr)
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{
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return (paddr >> (PAGE_SHIFT-1)) | 1;
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}
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/* Return the minimum of MAX or the first power of two larger
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than main memory. */
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unsigned long
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size_for_memory(unsigned long max)
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{
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unsigned long mem = max_low_pfn << PAGE_SHIFT;
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if (mem < max)
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max = roundup_pow_of_two(mem);
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return max;
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}
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struct pci_iommu_arena * __init
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iommu_arena_new_node(int nid, struct pci_controller *hose, dma_addr_t base,
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unsigned long window_size, unsigned long align)
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{
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unsigned long mem_size;
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struct pci_iommu_arena *arena;
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mem_size = window_size / (PAGE_SIZE / sizeof(unsigned long));
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/* Note that the TLB lookup logic uses bitwise concatenation,
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not addition, so the required arena alignment is based on
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the size of the window. Retain the align parameter so that
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particular systems can over-align the arena. */
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if (align < mem_size)
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align = mem_size;
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#ifdef CONFIG_DISCONTIGMEM
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arena = alloc_bootmem_node(NODE_DATA(nid), sizeof(*arena));
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if (!NODE_DATA(nid) || !arena) {
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printk("%s: couldn't allocate arena from node %d\n"
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" falling back to system-wide allocation\n",
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__func__, nid);
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arena = alloc_bootmem(sizeof(*arena));
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}
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arena->ptes = __alloc_bootmem_node(NODE_DATA(nid), mem_size, align, 0);
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if (!NODE_DATA(nid) || !arena->ptes) {
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printk("%s: couldn't allocate arena ptes from node %d\n"
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" falling back to system-wide allocation\n",
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__func__, nid);
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arena->ptes = __alloc_bootmem(mem_size, align, 0);
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}
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#else /* CONFIG_DISCONTIGMEM */
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arena = alloc_bootmem(sizeof(*arena));
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arena->ptes = __alloc_bootmem(mem_size, align, 0);
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#endif /* CONFIG_DISCONTIGMEM */
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spin_lock_init(&arena->lock);
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arena->hose = hose;
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arena->dma_base = base;
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arena->size = window_size;
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arena->next_entry = 0;
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/* Align allocations to a multiple of a page size. Not needed
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unless there are chip bugs. */
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arena->align_entry = 1;
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return arena;
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}
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struct pci_iommu_arena * __init
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iommu_arena_new(struct pci_controller *hose, dma_addr_t base,
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unsigned long window_size, unsigned long align)
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{
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return iommu_arena_new_node(0, hose, base, window_size, align);
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}
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/* Must be called with the arena lock held */
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static long
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iommu_arena_find_pages(struct device *dev, struct pci_iommu_arena *arena,
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long n, long mask)
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{
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unsigned long *ptes;
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long i, p, nent;
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int pass = 0;
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unsigned long base;
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unsigned long boundary_size;
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base = arena->dma_base >> PAGE_SHIFT;
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if (dev) {
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boundary_size = dma_get_seg_boundary(dev) + 1;
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boundary_size >>= PAGE_SHIFT;
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} else {
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boundary_size = 1UL << (32 - PAGE_SHIFT);
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}
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/* Search forward for the first mask-aligned sequence of N free ptes */
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ptes = arena->ptes;
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nent = arena->size >> PAGE_SHIFT;
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p = ALIGN(arena->next_entry, mask + 1);
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i = 0;
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again:
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while (i < n && p+i < nent) {
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if (!i && iommu_is_span_boundary(p, n, base, boundary_size)) {
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p = ALIGN(p + 1, mask + 1);
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goto again;
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}
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if (ptes[p+i])
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p = ALIGN(p + i + 1, mask + 1), i = 0;
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else
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i = i + 1;
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}
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if (i < n) {
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if (pass < 1) {
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/*
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* Reached the end. Flush the TLB and restart
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* the search from the beginning.
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*/
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alpha_mv.mv_pci_tbi(arena->hose, 0, -1);
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pass++;
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p = 0;
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i = 0;
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goto again;
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} else
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return -1;
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}
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/* Success. It's the responsibility of the caller to mark them
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in use before releasing the lock */
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return p;
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}
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static long
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iommu_arena_alloc(struct device *dev, struct pci_iommu_arena *arena, long n,
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unsigned int align)
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{
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unsigned long flags;
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unsigned long *ptes;
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long i, p, mask;
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spin_lock_irqsave(&arena->lock, flags);
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/* Search for N empty ptes */
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ptes = arena->ptes;
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mask = max(align, arena->align_entry) - 1;
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p = iommu_arena_find_pages(dev, arena, n, mask);
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if (p < 0) {
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spin_unlock_irqrestore(&arena->lock, flags);
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return -1;
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}
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/* Success. Mark them all in use, ie not zero and invalid
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for the iommu tlb that could load them from under us.
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The chip specific bits will fill this in with something
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kosher when we return. */
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for (i = 0; i < n; ++i)
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ptes[p+i] = IOMMU_INVALID_PTE;
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arena->next_entry = p + n;
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spin_unlock_irqrestore(&arena->lock, flags);
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return p;
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}
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static void
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iommu_arena_free(struct pci_iommu_arena *arena, long ofs, long n)
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{
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unsigned long *p;
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long i;
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p = arena->ptes + ofs;
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for (i = 0; i < n; ++i)
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p[i] = 0;
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}
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/*
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* True if the machine supports DAC addressing, and DEV can
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* make use of it given MASK.
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*/
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static int pci_dac_dma_supported(struct pci_dev *dev, u64 mask)
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{
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dma64_addr_t dac_offset = alpha_mv.pci_dac_offset;
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int ok = 1;
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/* If this is not set, the machine doesn't support DAC at all. */
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if (dac_offset == 0)
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ok = 0;
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/* The device has to be able to address our DAC bit. */
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if ((dac_offset & dev->dma_mask) != dac_offset)
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ok = 0;
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/* If both conditions above are met, we are fine. */
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DBGA("pci_dac_dma_supported %s from %p\n",
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ok ? "yes" : "no", __builtin_return_address(0));
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return ok;
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}
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/* Map a single buffer of the indicated size for PCI DMA in streaming
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mode. The 32-bit PCI bus mastering address to use is returned.
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Once the device is given the dma address, the device owns this memory
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until either pci_unmap_single or pci_dma_sync_single is performed. */
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static dma_addr_t
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pci_map_single_1(struct pci_dev *pdev, void *cpu_addr, size_t size,
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int dac_allowed)
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{
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struct pci_controller *hose = pdev ? pdev->sysdata : pci_isa_hose;
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dma_addr_t max_dma = pdev ? pdev->dma_mask : ISA_DMA_MASK;
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struct pci_iommu_arena *arena;
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long npages, dma_ofs, i;
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unsigned long paddr;
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dma_addr_t ret;
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unsigned int align = 0;
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struct device *dev = pdev ? &pdev->dev : NULL;
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paddr = __pa(cpu_addr);
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#if !DEBUG_NODIRECT
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/* First check to see if we can use the direct map window. */
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if (paddr + size + __direct_map_base - 1 <= max_dma
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&& paddr + size <= __direct_map_size) {
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ret = paddr + __direct_map_base;
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DBGA2("pci_map_single: [%p,%zx] -> direct %llx from %p\n",
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cpu_addr, size, ret, __builtin_return_address(0));
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return ret;
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}
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#endif
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/* Next, use DAC if selected earlier. */
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if (dac_allowed) {
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ret = paddr + alpha_mv.pci_dac_offset;
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DBGA2("pci_map_single: [%p,%zx] -> DAC %llx from %p\n",
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cpu_addr, size, ret, __builtin_return_address(0));
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return ret;
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}
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/* If the machine doesn't define a pci_tbi routine, we have to
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assume it doesn't support sg mapping, and, since we tried to
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use direct_map above, it now must be considered an error. */
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if (! alpha_mv.mv_pci_tbi) {
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printk_once(KERN_WARNING "pci_map_single: no HW sg\n");
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return 0;
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}
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arena = hose->sg_pci;
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if (!arena || arena->dma_base + arena->size - 1 > max_dma)
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arena = hose->sg_isa;
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npages = iommu_num_pages(paddr, size, PAGE_SIZE);
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/* Force allocation to 64KB boundary for ISA bridges. */
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if (pdev && pdev == isa_bridge)
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align = 8;
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dma_ofs = iommu_arena_alloc(dev, arena, npages, align);
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if (dma_ofs < 0) {
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printk(KERN_WARNING "pci_map_single failed: "
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"could not allocate dma page tables\n");
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return 0;
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}
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paddr &= PAGE_MASK;
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for (i = 0; i < npages; ++i, paddr += PAGE_SIZE)
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arena->ptes[i + dma_ofs] = mk_iommu_pte(paddr);
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ret = arena->dma_base + dma_ofs * PAGE_SIZE;
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ret += (unsigned long)cpu_addr & ~PAGE_MASK;
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DBGA2("pci_map_single: [%p,%zx] np %ld -> sg %llx from %p\n",
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cpu_addr, size, npages, ret, __builtin_return_address(0));
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return ret;
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}
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/* Helper for generic DMA-mapping functions. */
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static struct pci_dev *alpha_gendev_to_pci(struct device *dev)
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{
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if (dev && dev->bus == &pci_bus_type)
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return to_pci_dev(dev);
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/* Assume that non-PCI devices asking for DMA are either ISA or EISA,
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BUG() otherwise. */
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BUG_ON(!isa_bridge);
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/* Assume non-busmaster ISA DMA when dma_mask is not set (the ISA
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bridge is bus master then). */
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if (!dev || !dev->dma_mask || !*dev->dma_mask)
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return isa_bridge;
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/* For EISA bus masters, return isa_bridge (it might have smaller
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dma_mask due to wiring limitations). */
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if (*dev->dma_mask >= isa_bridge->dma_mask)
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return isa_bridge;
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/* This assumes ISA bus master with dma_mask 0xffffff. */
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return NULL;
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}
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static dma_addr_t alpha_pci_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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struct pci_dev *pdev = alpha_gendev_to_pci(dev);
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int dac_allowed;
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|
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if (dir == PCI_DMA_NONE)
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BUG();
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dac_allowed = pdev ? pci_dac_dma_supported(pdev, pdev->dma_mask) : 0;
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return pci_map_single_1(pdev, (char *)page_address(page) + offset,
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size, dac_allowed);
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}
|
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|
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/* Unmap a single streaming mode DMA translation. The DMA_ADDR and
|
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SIZE must match what was provided for in a previous pci_map_single
|
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call. All other usages are undefined. After this call, reads by
|
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the cpu to the buffer are guaranteed to see whatever the device
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wrote there. */
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|
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static void alpha_pci_unmap_page(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs)
|
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{
|
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unsigned long flags;
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struct pci_dev *pdev = alpha_gendev_to_pci(dev);
|
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struct pci_controller *hose = pdev ? pdev->sysdata : pci_isa_hose;
|
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struct pci_iommu_arena *arena;
|
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long dma_ofs, npages;
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|
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if (dir == PCI_DMA_NONE)
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BUG();
|
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|
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if (dma_addr >= __direct_map_base
|
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&& dma_addr < __direct_map_base + __direct_map_size) {
|
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/* Nothing to do. */
|
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|
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DBGA2("pci_unmap_single: direct [%llx,%zx] from %p\n",
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dma_addr, size, __builtin_return_address(0));
|
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|
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return;
|
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}
|
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|
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if (dma_addr > 0xffffffff) {
|
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DBGA2("pci64_unmap_single: DAC [%llx,%zx] from %p\n",
|
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dma_addr, size, __builtin_return_address(0));
|
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return;
|
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}
|
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|
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arena = hose->sg_pci;
|
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if (!arena || dma_addr < arena->dma_base)
|
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arena = hose->sg_isa;
|
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|
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dma_ofs = (dma_addr - arena->dma_base) >> PAGE_SHIFT;
|
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if (dma_ofs * PAGE_SIZE >= arena->size) {
|
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printk(KERN_ERR "Bogus pci_unmap_single: dma_addr %llx "
|
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" base %llx size %x\n",
|
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dma_addr, arena->dma_base, arena->size);
|
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return;
|
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BUG();
|
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}
|
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|
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npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
|
||
|
||
spin_lock_irqsave(&arena->lock, flags);
|
||
|
||
iommu_arena_free(arena, dma_ofs, npages);
|
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|
||
/* If we're freeing ptes above the `next_entry' pointer (they
|
||
may have snuck back into the TLB since the last wrap flush),
|
||
we need to flush the TLB before reallocating the latter. */
|
||
if (dma_ofs >= arena->next_entry)
|
||
alpha_mv.mv_pci_tbi(hose, dma_addr, dma_addr + size - 1);
|
||
|
||
spin_unlock_irqrestore(&arena->lock, flags);
|
||
|
||
DBGA2("pci_unmap_single: sg [%llx,%zx] np %ld from %p\n",
|
||
dma_addr, size, npages, __builtin_return_address(0));
|
||
}
|
||
|
||
/* Allocate and map kernel buffer using consistent mode DMA for PCI
|
||
device. Returns non-NULL cpu-view pointer to the buffer if
|
||
successful and sets *DMA_ADDRP to the pci side dma address as well,
|
||
else DMA_ADDRP is undefined. */
|
||
|
||
static void *alpha_pci_alloc_coherent(struct device *dev, size_t size,
|
||
dma_addr_t *dma_addrp, gfp_t gfp)
|
||
{
|
||
struct pci_dev *pdev = alpha_gendev_to_pci(dev);
|
||
void *cpu_addr;
|
||
long order = get_order(size);
|
||
|
||
gfp &= ~GFP_DMA;
|
||
|
||
try_again:
|
||
cpu_addr = (void *)__get_free_pages(gfp, order);
|
||
if (! cpu_addr) {
|
||
printk(KERN_INFO "pci_alloc_consistent: "
|
||
"get_free_pages failed from %p\n",
|
||
__builtin_return_address(0));
|
||
/* ??? Really atomic allocation? Otherwise we could play
|
||
with vmalloc and sg if we can't find contiguous memory. */
|
||
return NULL;
|
||
}
|
||
memset(cpu_addr, 0, size);
|
||
|
||
*dma_addrp = pci_map_single_1(pdev, cpu_addr, size, 0);
|
||
if (*dma_addrp == 0) {
|
||
free_pages((unsigned long)cpu_addr, order);
|
||
if (alpha_mv.mv_pci_tbi || (gfp & GFP_DMA))
|
||
return NULL;
|
||
/* The address doesn't fit required mask and we
|
||
do not have iommu. Try again with GFP_DMA. */
|
||
gfp |= GFP_DMA;
|
||
goto try_again;
|
||
}
|
||
|
||
DBGA2("pci_alloc_consistent: %zx -> [%p,%llx] from %p\n",
|
||
size, cpu_addr, *dma_addrp, __builtin_return_address(0));
|
||
|
||
return cpu_addr;
|
||
}
|
||
|
||
/* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must
|
||
be values that were returned from pci_alloc_consistent. SIZE must
|
||
be the same as what as passed into pci_alloc_consistent.
|
||
References to the memory and mappings associated with CPU_ADDR or
|
||
DMA_ADDR past this call are illegal. */
|
||
|
||
static void alpha_pci_free_coherent(struct device *dev, size_t size,
|
||
void *cpu_addr, dma_addr_t dma_addr)
|
||
{
|
||
struct pci_dev *pdev = alpha_gendev_to_pci(dev);
|
||
pci_unmap_single(pdev, dma_addr, size, PCI_DMA_BIDIRECTIONAL);
|
||
free_pages((unsigned long)cpu_addr, get_order(size));
|
||
|
||
DBGA2("pci_free_consistent: [%llx,%zx] from %p\n",
|
||
dma_addr, size, __builtin_return_address(0));
|
||
}
|
||
|
||
/* Classify the elements of the scatterlist. Write dma_address
|
||
of each element with:
|
||
0 : Followers all physically adjacent.
|
||
1 : Followers all virtually adjacent.
|
||
-1 : Not leader, physically adjacent to previous.
|
||
-2 : Not leader, virtually adjacent to previous.
|
||
Write dma_length of each leader with the combined lengths of
|
||
the mergable followers. */
|
||
|
||
#define SG_ENT_VIRT_ADDRESS(SG) (sg_virt((SG)))
|
||
#define SG_ENT_PHYS_ADDRESS(SG) __pa(SG_ENT_VIRT_ADDRESS(SG))
|
||
|
||
static void
|
||
sg_classify(struct device *dev, struct scatterlist *sg, struct scatterlist *end,
|
||
int virt_ok)
|
||
{
|
||
unsigned long next_paddr;
|
||
struct scatterlist *leader;
|
||
long leader_flag, leader_length;
|
||
unsigned int max_seg_size;
|
||
|
||
leader = sg;
|
||
leader_flag = 0;
|
||
leader_length = leader->length;
|
||
next_paddr = SG_ENT_PHYS_ADDRESS(leader) + leader_length;
|
||
|
||
/* we will not marge sg without device. */
|
||
max_seg_size = dev ? dma_get_max_seg_size(dev) : 0;
|
||
for (++sg; sg < end; ++sg) {
|
||
unsigned long addr, len;
|
||
addr = SG_ENT_PHYS_ADDRESS(sg);
|
||
len = sg->length;
|
||
|
||
if (leader_length + len > max_seg_size)
|
||
goto new_segment;
|
||
|
||
if (next_paddr == addr) {
|
||
sg->dma_address = -1;
|
||
leader_length += len;
|
||
} else if (((next_paddr | addr) & ~PAGE_MASK) == 0 && virt_ok) {
|
||
sg->dma_address = -2;
|
||
leader_flag = 1;
|
||
leader_length += len;
|
||
} else {
|
||
new_segment:
|
||
leader->dma_address = leader_flag;
|
||
leader->dma_length = leader_length;
|
||
leader = sg;
|
||
leader_flag = 0;
|
||
leader_length = len;
|
||
}
|
||
|
||
next_paddr = addr + len;
|
||
}
|
||
|
||
leader->dma_address = leader_flag;
|
||
leader->dma_length = leader_length;
|
||
}
|
||
|
||
/* Given a scatterlist leader, choose an allocation method and fill
|
||
in the blanks. */
|
||
|
||
static int
|
||
sg_fill(struct device *dev, struct scatterlist *leader, struct scatterlist *end,
|
||
struct scatterlist *out, struct pci_iommu_arena *arena,
|
||
dma_addr_t max_dma, int dac_allowed)
|
||
{
|
||
unsigned long paddr = SG_ENT_PHYS_ADDRESS(leader);
|
||
long size = leader->dma_length;
|
||
struct scatterlist *sg;
|
||
unsigned long *ptes;
|
||
long npages, dma_ofs, i;
|
||
|
||
#if !DEBUG_NODIRECT
|
||
/* If everything is physically contiguous, and the addresses
|
||
fall into the direct-map window, use it. */
|
||
if (leader->dma_address == 0
|
||
&& paddr + size + __direct_map_base - 1 <= max_dma
|
||
&& paddr + size <= __direct_map_size) {
|
||
out->dma_address = paddr + __direct_map_base;
|
||
out->dma_length = size;
|
||
|
||
DBGA(" sg_fill: [%p,%lx] -> direct %llx\n",
|
||
__va(paddr), size, out->dma_address);
|
||
|
||
return 0;
|
||
}
|
||
#endif
|
||
|
||
/* If physically contiguous and DAC is available, use it. */
|
||
if (leader->dma_address == 0 && dac_allowed) {
|
||
out->dma_address = paddr + alpha_mv.pci_dac_offset;
|
||
out->dma_length = size;
|
||
|
||
DBGA(" sg_fill: [%p,%lx] -> DAC %llx\n",
|
||
__va(paddr), size, out->dma_address);
|
||
|
||
return 0;
|
||
}
|
||
|
||
/* Otherwise, we'll use the iommu to make the pages virtually
|
||
contiguous. */
|
||
|
||
paddr &= ~PAGE_MASK;
|
||
npages = iommu_num_pages(paddr, size, PAGE_SIZE);
|
||
dma_ofs = iommu_arena_alloc(dev, arena, npages, 0);
|
||
if (dma_ofs < 0) {
|
||
/* If we attempted a direct map above but failed, die. */
|
||
if (leader->dma_address == 0)
|
||
return -1;
|
||
|
||
/* Otherwise, break up the remaining virtually contiguous
|
||
hunks into individual direct maps and retry. */
|
||
sg_classify(dev, leader, end, 0);
|
||
return sg_fill(dev, leader, end, out, arena, max_dma, dac_allowed);
|
||
}
|
||
|
||
out->dma_address = arena->dma_base + dma_ofs*PAGE_SIZE + paddr;
|
||
out->dma_length = size;
|
||
|
||
DBGA(" sg_fill: [%p,%lx] -> sg %llx np %ld\n",
|
||
__va(paddr), size, out->dma_address, npages);
|
||
|
||
/* All virtually contiguous. We need to find the length of each
|
||
physically contiguous subsegment to fill in the ptes. */
|
||
ptes = &arena->ptes[dma_ofs];
|
||
sg = leader;
|
||
do {
|
||
#if DEBUG_ALLOC > 0
|
||
struct scatterlist *last_sg = sg;
|
||
#endif
|
||
|
||
size = sg->length;
|
||
paddr = SG_ENT_PHYS_ADDRESS(sg);
|
||
|
||
while (sg+1 < end && (int) sg[1].dma_address == -1) {
|
||
size += sg[1].length;
|
||
sg++;
|
||
}
|
||
|
||
npages = iommu_num_pages(paddr, size, PAGE_SIZE);
|
||
|
||
paddr &= PAGE_MASK;
|
||
for (i = 0; i < npages; ++i, paddr += PAGE_SIZE)
|
||
*ptes++ = mk_iommu_pte(paddr);
|
||
|
||
#if DEBUG_ALLOC > 0
|
||
DBGA(" (%ld) [%p,%x] np %ld\n",
|
||
last_sg - leader, SG_ENT_VIRT_ADDRESS(last_sg),
|
||
last_sg->length, npages);
|
||
while (++last_sg <= sg) {
|
||
DBGA(" (%ld) [%p,%x] cont\n",
|
||
last_sg - leader, SG_ENT_VIRT_ADDRESS(last_sg),
|
||
last_sg->length);
|
||
}
|
||
#endif
|
||
} while (++sg < end && (int) sg->dma_address < 0);
|
||
|
||
return 1;
|
||
}
|
||
|
||
static int alpha_pci_map_sg(struct device *dev, struct scatterlist *sg,
|
||
int nents, enum dma_data_direction dir,
|
||
struct dma_attrs *attrs)
|
||
{
|
||
struct pci_dev *pdev = alpha_gendev_to_pci(dev);
|
||
struct scatterlist *start, *end, *out;
|
||
struct pci_controller *hose;
|
||
struct pci_iommu_arena *arena;
|
||
dma_addr_t max_dma;
|
||
int dac_allowed;
|
||
|
||
if (dir == PCI_DMA_NONE)
|
||
BUG();
|
||
|
||
dac_allowed = dev ? pci_dac_dma_supported(pdev, pdev->dma_mask) : 0;
|
||
|
||
/* Fast path single entry scatterlists. */
|
||
if (nents == 1) {
|
||
sg->dma_length = sg->length;
|
||
sg->dma_address
|
||
= pci_map_single_1(pdev, SG_ENT_VIRT_ADDRESS(sg),
|
||
sg->length, dac_allowed);
|
||
return sg->dma_address != 0;
|
||
}
|
||
|
||
start = sg;
|
||
end = sg + nents;
|
||
|
||
/* First, prepare information about the entries. */
|
||
sg_classify(dev, sg, end, alpha_mv.mv_pci_tbi != 0);
|
||
|
||
/* Second, figure out where we're going to map things. */
|
||
if (alpha_mv.mv_pci_tbi) {
|
||
hose = pdev ? pdev->sysdata : pci_isa_hose;
|
||
max_dma = pdev ? pdev->dma_mask : ISA_DMA_MASK;
|
||
arena = hose->sg_pci;
|
||
if (!arena || arena->dma_base + arena->size - 1 > max_dma)
|
||
arena = hose->sg_isa;
|
||
} else {
|
||
max_dma = -1;
|
||
arena = NULL;
|
||
hose = NULL;
|
||
}
|
||
|
||
/* Third, iterate over the scatterlist leaders and allocate
|
||
dma space as needed. */
|
||
for (out = sg; sg < end; ++sg) {
|
||
if ((int) sg->dma_address < 0)
|
||
continue;
|
||
if (sg_fill(dev, sg, end, out, arena, max_dma, dac_allowed) < 0)
|
||
goto error;
|
||
out++;
|
||
}
|
||
|
||
/* Mark the end of the list for pci_unmap_sg. */
|
||
if (out < end)
|
||
out->dma_length = 0;
|
||
|
||
if (out - start == 0)
|
||
printk(KERN_WARNING "pci_map_sg failed: no entries?\n");
|
||
DBGA("pci_map_sg: %ld entries\n", out - start);
|
||
|
||
return out - start;
|
||
|
||
error:
|
||
printk(KERN_WARNING "pci_map_sg failed: "
|
||
"could not allocate dma page tables\n");
|
||
|
||
/* Some allocation failed while mapping the scatterlist
|
||
entries. Unmap them now. */
|
||
if (out > start)
|
||
pci_unmap_sg(pdev, start, out - start, dir);
|
||
return 0;
|
||
}
|
||
|
||
/* Unmap a set of streaming mode DMA translations. Again, cpu read
|
||
rules concerning calls here are the same as for pci_unmap_single()
|
||
above. */
|
||
|
||
static void alpha_pci_unmap_sg(struct device *dev, struct scatterlist *sg,
|
||
int nents, enum dma_data_direction dir,
|
||
struct dma_attrs *attrs)
|
||
{
|
||
struct pci_dev *pdev = alpha_gendev_to_pci(dev);
|
||
unsigned long flags;
|
||
struct pci_controller *hose;
|
||
struct pci_iommu_arena *arena;
|
||
struct scatterlist *end;
|
||
dma_addr_t max_dma;
|
||
dma_addr_t fbeg, fend;
|
||
|
||
if (dir == PCI_DMA_NONE)
|
||
BUG();
|
||
|
||
if (! alpha_mv.mv_pci_tbi)
|
||
return;
|
||
|
||
hose = pdev ? pdev->sysdata : pci_isa_hose;
|
||
max_dma = pdev ? pdev->dma_mask : ISA_DMA_MASK;
|
||
arena = hose->sg_pci;
|
||
if (!arena || arena->dma_base + arena->size - 1 > max_dma)
|
||
arena = hose->sg_isa;
|
||
|
||
fbeg = -1, fend = 0;
|
||
|
||
spin_lock_irqsave(&arena->lock, flags);
|
||
|
||
for (end = sg + nents; sg < end; ++sg) {
|
||
dma64_addr_t addr;
|
||
size_t size;
|
||
long npages, ofs;
|
||
dma_addr_t tend;
|
||
|
||
addr = sg->dma_address;
|
||
size = sg->dma_length;
|
||
if (!size)
|
||
break;
|
||
|
||
if (addr > 0xffffffff) {
|
||
/* It's a DAC address -- nothing to do. */
|
||
DBGA(" (%ld) DAC [%llx,%zx]\n",
|
||
sg - end + nents, addr, size);
|
||
continue;
|
||
}
|
||
|
||
if (addr >= __direct_map_base
|
||
&& addr < __direct_map_base + __direct_map_size) {
|
||
/* Nothing to do. */
|
||
DBGA(" (%ld) direct [%llx,%zx]\n",
|
||
sg - end + nents, addr, size);
|
||
continue;
|
||
}
|
||
|
||
DBGA(" (%ld) sg [%llx,%zx]\n",
|
||
sg - end + nents, addr, size);
|
||
|
||
npages = iommu_num_pages(addr, size, PAGE_SIZE);
|
||
ofs = (addr - arena->dma_base) >> PAGE_SHIFT;
|
||
iommu_arena_free(arena, ofs, npages);
|
||
|
||
tend = addr + size - 1;
|
||
if (fbeg > addr) fbeg = addr;
|
||
if (fend < tend) fend = tend;
|
||
}
|
||
|
||
/* If we're freeing ptes above the `next_entry' pointer (they
|
||
may have snuck back into the TLB since the last wrap flush),
|
||
we need to flush the TLB before reallocating the latter. */
|
||
if ((fend - arena->dma_base) >> PAGE_SHIFT >= arena->next_entry)
|
||
alpha_mv.mv_pci_tbi(hose, fbeg, fend);
|
||
|
||
spin_unlock_irqrestore(&arena->lock, flags);
|
||
|
||
DBGA("pci_unmap_sg: %ld entries\n", nents - (end - sg));
|
||
}
|
||
|
||
/* Return whether the given PCI device DMA address mask can be
|
||
supported properly. */
|
||
|
||
static int alpha_pci_supported(struct device *dev, u64 mask)
|
||
{
|
||
struct pci_dev *pdev = alpha_gendev_to_pci(dev);
|
||
struct pci_controller *hose;
|
||
struct pci_iommu_arena *arena;
|
||
|
||
/* If there exists a direct map, and the mask fits either
|
||
the entire direct mapped space or the total system memory as
|
||
shifted by the map base */
|
||
if (__direct_map_size != 0
|
||
&& (__direct_map_base + __direct_map_size - 1 <= mask ||
|
||
__direct_map_base + (max_low_pfn << PAGE_SHIFT) - 1 <= mask))
|
||
return 1;
|
||
|
||
/* Check that we have a scatter-gather arena that fits. */
|
||
hose = pdev ? pdev->sysdata : pci_isa_hose;
|
||
arena = hose->sg_isa;
|
||
if (arena && arena->dma_base + arena->size - 1 <= mask)
|
||
return 1;
|
||
arena = hose->sg_pci;
|
||
if (arena && arena->dma_base + arena->size - 1 <= mask)
|
||
return 1;
|
||
|
||
/* As last resort try ZONE_DMA. */
|
||
if (!__direct_map_base && MAX_DMA_ADDRESS - IDENT_ADDR - 1 <= mask)
|
||
return 1;
|
||
|
||
return 0;
|
||
}
|
||
|
||
|
||
/*
|
||
* AGP GART extensions to the IOMMU
|
||
*/
|
||
int
|
||
iommu_reserve(struct pci_iommu_arena *arena, long pg_count, long align_mask)
|
||
{
|
||
unsigned long flags;
|
||
unsigned long *ptes;
|
||
long i, p;
|
||
|
||
if (!arena) return -EINVAL;
|
||
|
||
spin_lock_irqsave(&arena->lock, flags);
|
||
|
||
/* Search for N empty ptes. */
|
||
ptes = arena->ptes;
|
||
p = iommu_arena_find_pages(NULL, arena, pg_count, align_mask);
|
||
if (p < 0) {
|
||
spin_unlock_irqrestore(&arena->lock, flags);
|
||
return -1;
|
||
}
|
||
|
||
/* Success. Mark them all reserved (ie not zero and invalid)
|
||
for the iommu tlb that could load them from under us.
|
||
They will be filled in with valid bits by _bind() */
|
||
for (i = 0; i < pg_count; ++i)
|
||
ptes[p+i] = IOMMU_RESERVED_PTE;
|
||
|
||
arena->next_entry = p + pg_count;
|
||
spin_unlock_irqrestore(&arena->lock, flags);
|
||
|
||
return p;
|
||
}
|
||
|
||
int
|
||
iommu_release(struct pci_iommu_arena *arena, long pg_start, long pg_count)
|
||
{
|
||
unsigned long *ptes;
|
||
long i;
|
||
|
||
if (!arena) return -EINVAL;
|
||
|
||
ptes = arena->ptes;
|
||
|
||
/* Make sure they're all reserved first... */
|
||
for(i = pg_start; i < pg_start + pg_count; i++)
|
||
if (ptes[i] != IOMMU_RESERVED_PTE)
|
||
return -EBUSY;
|
||
|
||
iommu_arena_free(arena, pg_start, pg_count);
|
||
return 0;
|
||
}
|
||
|
||
int
|
||
iommu_bind(struct pci_iommu_arena *arena, long pg_start, long pg_count,
|
||
struct page **pages)
|
||
{
|
||
unsigned long flags;
|
||
unsigned long *ptes;
|
||
long i, j;
|
||
|
||
if (!arena) return -EINVAL;
|
||
|
||
spin_lock_irqsave(&arena->lock, flags);
|
||
|
||
ptes = arena->ptes;
|
||
|
||
for(j = pg_start; j < pg_start + pg_count; j++) {
|
||
if (ptes[j] != IOMMU_RESERVED_PTE) {
|
||
spin_unlock_irqrestore(&arena->lock, flags);
|
||
return -EBUSY;
|
||
}
|
||
}
|
||
|
||
for(i = 0, j = pg_start; i < pg_count; i++, j++)
|
||
ptes[j] = mk_iommu_pte(page_to_phys(pages[i]));
|
||
|
||
spin_unlock_irqrestore(&arena->lock, flags);
|
||
|
||
return 0;
|
||
}
|
||
|
||
int
|
||
iommu_unbind(struct pci_iommu_arena *arena, long pg_start, long pg_count)
|
||
{
|
||
unsigned long *p;
|
||
long i;
|
||
|
||
if (!arena) return -EINVAL;
|
||
|
||
p = arena->ptes + pg_start;
|
||
for(i = 0; i < pg_count; i++)
|
||
p[i] = IOMMU_RESERVED_PTE;
|
||
|
||
return 0;
|
||
}
|
||
|
||
static int alpha_pci_mapping_error(struct device *dev, dma_addr_t dma_addr)
|
||
{
|
||
return dma_addr == 0;
|
||
}
|
||
|
||
static int alpha_pci_set_mask(struct device *dev, u64 mask)
|
||
{
|
||
if (!dev->dma_mask ||
|
||
!pci_dma_supported(alpha_gendev_to_pci(dev), mask))
|
||
return -EIO;
|
||
|
||
*dev->dma_mask = mask;
|
||
return 0;
|
||
}
|
||
|
||
struct dma_map_ops alpha_pci_ops = {
|
||
.alloc_coherent = alpha_pci_alloc_coherent,
|
||
.free_coherent = alpha_pci_free_coherent,
|
||
.map_page = alpha_pci_map_page,
|
||
.unmap_page = alpha_pci_unmap_page,
|
||
.map_sg = alpha_pci_map_sg,
|
||
.unmap_sg = alpha_pci_unmap_sg,
|
||
.mapping_error = alpha_pci_mapping_error,
|
||
.dma_supported = alpha_pci_supported,
|
||
.set_dma_mask = alpha_pci_set_mask,
|
||
};
|
||
|
||
struct dma_map_ops *dma_ops = &alpha_pci_ops;
|
||
EXPORT_SYMBOL(dma_ops);
|