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![Kumar Gala](/assets/img/avatar_default.png)
The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
1565 lines
39 KiB
C
1565 lines
39 KiB
C
/*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Copyright 2007-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras (paulus@samba.org)
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*/
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/*
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* This file handles the architecture-dependent parts of hardware exceptions
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <linux/user.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/prctl.h>
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#include <linux/delay.h>
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#include <linux/kprobes.h>
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#include <linux/kexec.h>
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#include <linux/backlight.h>
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#include <linux/bug.h>
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#include <linux/kdebug.h>
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#include <linux/debugfs.h>
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#include <asm/emulated_ops.h>
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#include <asm/pgtable.h>
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#include <asm/uaccess.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/rtas.h>
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#include <asm/pmc.h>
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#ifdef CONFIG_PPC32
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#include <asm/reg.h>
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#endif
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#ifdef CONFIG_PMAC_BACKLIGHT
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#include <asm/backlight.h>
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#endif
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#ifdef CONFIG_PPC64
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#include <asm/firmware.h>
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#include <asm/processor.h>
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#endif
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#include <asm/kexec.h>
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#include <asm/ppc-opcode.h>
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#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
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int (*__debugger)(struct pt_regs *regs) __read_mostly;
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int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
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int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
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int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
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int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
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int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly;
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int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
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EXPORT_SYMBOL(__debugger);
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EXPORT_SYMBOL(__debugger_ipi);
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EXPORT_SYMBOL(__debugger_bpt);
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EXPORT_SYMBOL(__debugger_sstep);
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EXPORT_SYMBOL(__debugger_iabr_match);
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EXPORT_SYMBOL(__debugger_dabr_match);
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EXPORT_SYMBOL(__debugger_fault_handler);
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#endif
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/*
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* Trap & Exception support
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*/
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#ifdef CONFIG_PMAC_BACKLIGHT
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static void pmac_backlight_unblank(void)
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{
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mutex_lock(&pmac_backlight_mutex);
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if (pmac_backlight) {
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struct backlight_properties *props;
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props = &pmac_backlight->props;
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props->brightness = props->max_brightness;
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props->power = FB_BLANK_UNBLANK;
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backlight_update_status(pmac_backlight);
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}
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mutex_unlock(&pmac_backlight_mutex);
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}
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#else
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static inline void pmac_backlight_unblank(void) { }
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#endif
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int die(const char *str, struct pt_regs *regs, long err)
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{
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static struct {
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raw_spinlock_t lock;
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u32 lock_owner;
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int lock_owner_depth;
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} die = {
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.lock = __RAW_SPIN_LOCK_UNLOCKED(die.lock),
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.lock_owner = -1,
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.lock_owner_depth = 0
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};
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static int die_counter;
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unsigned long flags;
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if (debugger(regs))
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return 1;
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oops_enter();
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if (die.lock_owner != raw_smp_processor_id()) {
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console_verbose();
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raw_spin_lock_irqsave(&die.lock, flags);
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die.lock_owner = smp_processor_id();
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die.lock_owner_depth = 0;
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bust_spinlocks(1);
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if (machine_is(powermac))
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pmac_backlight_unblank();
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} else {
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local_save_flags(flags);
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}
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if (++die.lock_owner_depth < 3) {
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printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
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#ifdef CONFIG_PREEMPT
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printk("PREEMPT ");
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#endif
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#ifdef CONFIG_SMP
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printk("SMP NR_CPUS=%d ", NR_CPUS);
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#endif
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#ifdef CONFIG_DEBUG_PAGEALLOC
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printk("DEBUG_PAGEALLOC ");
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#endif
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#ifdef CONFIG_NUMA
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printk("NUMA ");
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#endif
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printk("%s\n", ppc_md.name ? ppc_md.name : "");
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sysfs_printk_last_file();
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if (notify_die(DIE_OOPS, str, regs, err, 255,
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SIGSEGV) == NOTIFY_STOP)
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return 1;
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print_modules();
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show_regs(regs);
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} else {
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printk("Recursive die() failure, output suppressed\n");
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}
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bust_spinlocks(0);
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die.lock_owner = -1;
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add_taint(TAINT_DIE);
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raw_spin_unlock_irqrestore(&die.lock, flags);
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if (kexec_should_crash(current) ||
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kexec_sr_activated(smp_processor_id()))
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crash_kexec(regs);
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crash_kexec_secondary(regs);
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if (in_interrupt())
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panic("Fatal exception in interrupt");
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if (panic_on_oops)
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panic("Fatal exception");
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oops_exit();
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do_exit(err);
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return 0;
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}
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void user_single_step_siginfo(struct task_struct *tsk,
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struct pt_regs *regs, siginfo_t *info)
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{
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memset(info, 0, sizeof(*info));
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info->si_signo = SIGTRAP;
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info->si_code = TRAP_TRACE;
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info->si_addr = (void __user *)regs->nip;
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}
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void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
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{
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siginfo_t info;
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const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
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"at %08lx nip %08lx lr %08lx code %x\n";
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const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
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"at %016lx nip %016lx lr %016lx code %x\n";
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if (!user_mode(regs)) {
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if (die("Exception in kernel mode", regs, signr))
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return;
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} else if (show_unhandled_signals &&
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unhandled_signal(current, signr) &&
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printk_ratelimit()) {
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printk(regs->msr & MSR_SF ? fmt64 : fmt32,
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current->comm, current->pid, signr,
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addr, regs->nip, regs->link, code);
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}
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memset(&info, 0, sizeof(info));
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info.si_signo = signr;
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info.si_code = code;
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info.si_addr = (void __user *) addr;
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force_sig_info(signr, &info, current);
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}
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#ifdef CONFIG_PPC64
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void system_reset_exception(struct pt_regs *regs)
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{
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/* See if any machine dependent calls */
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if (ppc_md.system_reset_exception) {
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if (ppc_md.system_reset_exception(regs))
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return;
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}
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#ifdef CONFIG_KEXEC
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cpu_set(smp_processor_id(), cpus_in_sr);
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#endif
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die("System Reset", regs, SIGABRT);
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/*
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* Some CPUs when released from the debugger will execute this path.
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* These CPUs entered the debugger via a soft-reset. If the CPU was
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* hung before entering the debugger it will return to the hung
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* state when exiting this function. This causes a problem in
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* kdump since the hung CPU(s) will not respond to the IPI sent
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* from kdump. To prevent the problem we call crash_kexec_secondary()
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* here. If a kdump had not been initiated or we exit the debugger
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* with the "exit and recover" command (x) crash_kexec_secondary()
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* will return after 5ms and the CPU returns to its previous state.
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*/
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crash_kexec_secondary(regs);
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/* Must die if the interrupt is not recoverable */
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if (!(regs->msr & MSR_RI))
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panic("Unrecoverable System Reset");
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/* What should we do here? We could issue a shutdown or hard reset. */
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}
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#endif
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/*
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* I/O accesses can cause machine checks on powermacs.
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* Check if the NIP corresponds to the address of a sync
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* instruction for which there is an entry in the exception
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* table.
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* Note that the 601 only takes a machine check on TEA
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* (transfer error ack) signal assertion, and does not
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* set any of the top 16 bits of SRR1.
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* -- paulus.
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*/
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static inline int check_io_access(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC32
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unsigned long msr = regs->msr;
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const struct exception_table_entry *entry;
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unsigned int *nip = (unsigned int *)regs->nip;
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if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
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&& (entry = search_exception_tables(regs->nip)) != NULL) {
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/*
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* Check that it's a sync instruction, or somewhere
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* in the twi; isync; nop sequence that inb/inw/inl uses.
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* As the address is in the exception table
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* we should be able to read the instr there.
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* For the debug message, we look at the preceding
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* load or store.
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*/
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if (*nip == 0x60000000) /* nop */
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nip -= 2;
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else if (*nip == 0x4c00012c) /* isync */
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--nip;
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if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
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/* sync or twi */
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unsigned int rb;
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--nip;
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rb = (*nip >> 11) & 0x1f;
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printk(KERN_DEBUG "%s bad port %lx at %p\n",
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(*nip & 0x100)? "OUT to": "IN from",
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regs->gpr[rb] - _IO_BASE, nip);
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regs->msr |= MSR_RI;
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regs->nip = entry->fixup;
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return 1;
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}
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}
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#endif /* CONFIG_PPC32 */
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return 0;
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}
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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/* On 4xx, the reason for the machine check or program exception
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is in the ESR. */
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#define get_reason(regs) ((regs)->dsisr)
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#ifndef CONFIG_FSL_BOOKE
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#define get_mc_reason(regs) ((regs)->dsisr)
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#else
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#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
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#endif
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#define REASON_FP ESR_FP
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#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
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#define REASON_PRIVILEGED ESR_PPR
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#define REASON_TRAP ESR_PTR
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/* single-step stuff */
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#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
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#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
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#else
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/* On non-4xx, the reason for the machine check or program
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exception is in the MSR. */
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#define get_reason(regs) ((regs)->msr)
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#define get_mc_reason(regs) ((regs)->msr)
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#define REASON_FP 0x100000
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#define REASON_ILLEGAL 0x80000
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#define REASON_PRIVILEGED 0x40000
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#define REASON_TRAP 0x20000
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#define single_stepping(regs) ((regs)->msr & MSR_SE)
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#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
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#endif
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#if defined(CONFIG_4xx)
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int machine_check_4xx(struct pt_regs *regs)
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{
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unsigned long reason = get_mc_reason(regs);
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if (reason & ESR_IMCP) {
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printk("Instruction");
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mtspr(SPRN_ESR, reason & ~ESR_IMCP);
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} else
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printk("Data");
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printk(" machine check in kernel mode.\n");
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return 0;
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}
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int machine_check_440A(struct pt_regs *regs)
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{
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unsigned long reason = get_mc_reason(regs);
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printk("Machine check in kernel mode.\n");
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if (reason & ESR_IMCP){
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printk("Instruction Synchronous Machine Check exception\n");
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mtspr(SPRN_ESR, reason & ~ESR_IMCP);
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}
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else {
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u32 mcsr = mfspr(SPRN_MCSR);
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if (mcsr & MCSR_IB)
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printk("Instruction Read PLB Error\n");
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if (mcsr & MCSR_DRB)
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printk("Data Read PLB Error\n");
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if (mcsr & MCSR_DWB)
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printk("Data Write PLB Error\n");
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if (mcsr & MCSR_TLBP)
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printk("TLB Parity Error\n");
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if (mcsr & MCSR_ICP){
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flush_instruction_cache();
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printk("I-Cache Parity Error\n");
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}
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if (mcsr & MCSR_DCSP)
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printk("D-Cache Search Parity Error\n");
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if (mcsr & MCSR_DCFP)
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printk("D-Cache Flush Parity Error\n");
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if (mcsr & MCSR_IMPE)
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printk("Machine Check exception is imprecise\n");
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/* Clear MCSR */
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mtspr(SPRN_MCSR, mcsr);
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}
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return 0;
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}
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int machine_check_47x(struct pt_regs *regs)
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{
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unsigned long reason = get_mc_reason(regs);
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u32 mcsr;
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printk(KERN_ERR "Machine check in kernel mode.\n");
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if (reason & ESR_IMCP) {
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printk(KERN_ERR
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"Instruction Synchronous Machine Check exception\n");
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mtspr(SPRN_ESR, reason & ~ESR_IMCP);
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return 0;
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}
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mcsr = mfspr(SPRN_MCSR);
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if (mcsr & MCSR_IB)
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printk(KERN_ERR "Instruction Read PLB Error\n");
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if (mcsr & MCSR_DRB)
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printk(KERN_ERR "Data Read PLB Error\n");
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if (mcsr & MCSR_DWB)
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printk(KERN_ERR "Data Write PLB Error\n");
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if (mcsr & MCSR_TLBP)
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printk(KERN_ERR "TLB Parity Error\n");
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if (mcsr & MCSR_ICP) {
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flush_instruction_cache();
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printk(KERN_ERR "I-Cache Parity Error\n");
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}
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if (mcsr & MCSR_DCSP)
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printk(KERN_ERR "D-Cache Search Parity Error\n");
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if (mcsr & PPC47x_MCSR_GPR)
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printk(KERN_ERR "GPR Parity Error\n");
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if (mcsr & PPC47x_MCSR_FPR)
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printk(KERN_ERR "FPR Parity Error\n");
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if (mcsr & PPC47x_MCSR_IPR)
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printk(KERN_ERR "Machine Check exception is imprecise\n");
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/* Clear MCSR */
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mtspr(SPRN_MCSR, mcsr);
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return 0;
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}
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#elif defined(CONFIG_E500)
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int machine_check_e500mc(struct pt_regs *regs)
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{
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unsigned long mcsr = mfspr(SPRN_MCSR);
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unsigned long reason = mcsr;
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int recoverable = 1;
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printk("Machine check in kernel mode.\n");
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printk("Caused by (from MCSR=%lx): ", reason);
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if (reason & MCSR_MCP)
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printk("Machine Check Signal\n");
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if (reason & MCSR_ICPERR) {
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printk("Instruction Cache Parity Error\n");
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/*
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* This is recoverable by invalidating the i-cache.
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*/
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mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
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while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
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;
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/*
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* This will generally be accompanied by an instruction
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* fetch error report -- only treat MCSR_IF as fatal
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* if it wasn't due to an L1 parity error.
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*/
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reason &= ~MCSR_IF;
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}
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if (reason & MCSR_DCPERR_MC) {
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printk("Data Cache Parity Error\n");
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recoverable = 0;
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}
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if (reason & MCSR_L2MMU_MHIT) {
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printk("Hit on multiple TLB entries\n");
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recoverable = 0;
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}
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if (reason & MCSR_NMI)
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printk("Non-maskable interrupt\n");
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if (reason & MCSR_IF) {
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printk("Instruction Fetch Error Report\n");
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recoverable = 0;
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}
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if (reason & MCSR_LD) {
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printk("Load Error Report\n");
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recoverable = 0;
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}
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if (reason & MCSR_ST) {
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printk("Store Error Report\n");
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recoverable = 0;
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}
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if (reason & MCSR_LDG) {
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printk("Guarded Load Error Report\n");
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recoverable = 0;
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}
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if (reason & MCSR_TLBSYNC)
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printk("Simultaneous tlbsync operations\n");
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if (reason & MCSR_BSL2_ERR) {
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printk("Level 2 Cache Error\n");
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recoverable = 0;
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}
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|
|
|
if (reason & MCSR_MAV) {
|
|
u64 addr;
|
|
|
|
addr = mfspr(SPRN_MCAR);
|
|
addr |= (u64)mfspr(SPRN_MCARU) << 32;
|
|
|
|
printk("Machine Check %s Address: %#llx\n",
|
|
reason & MCSR_MEA ? "Effective" : "Physical", addr);
|
|
}
|
|
|
|
mtspr(SPRN_MCSR, mcsr);
|
|
return mfspr(SPRN_MCSR) == 0 && recoverable;
|
|
}
|
|
|
|
int machine_check_e500(struct pt_regs *regs)
|
|
{
|
|
unsigned long reason = get_mc_reason(regs);
|
|
|
|
printk("Machine check in kernel mode.\n");
|
|
printk("Caused by (from MCSR=%lx): ", reason);
|
|
|
|
if (reason & MCSR_MCP)
|
|
printk("Machine Check Signal\n");
|
|
if (reason & MCSR_ICPERR)
|
|
printk("Instruction Cache Parity Error\n");
|
|
if (reason & MCSR_DCP_PERR)
|
|
printk("Data Cache Push Parity Error\n");
|
|
if (reason & MCSR_DCPERR)
|
|
printk("Data Cache Parity Error\n");
|
|
if (reason & MCSR_BUS_IAERR)
|
|
printk("Bus - Instruction Address Error\n");
|
|
if (reason & MCSR_BUS_RAERR)
|
|
printk("Bus - Read Address Error\n");
|
|
if (reason & MCSR_BUS_WAERR)
|
|
printk("Bus - Write Address Error\n");
|
|
if (reason & MCSR_BUS_IBERR)
|
|
printk("Bus - Instruction Data Error\n");
|
|
if (reason & MCSR_BUS_RBERR)
|
|
printk("Bus - Read Data Bus Error\n");
|
|
if (reason & MCSR_BUS_WBERR)
|
|
printk("Bus - Read Data Bus Error\n");
|
|
if (reason & MCSR_BUS_IPERR)
|
|
printk("Bus - Instruction Parity Error\n");
|
|
if (reason & MCSR_BUS_RPERR)
|
|
printk("Bus - Read Parity Error\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
int machine_check_generic(struct pt_regs *regs)
|
|
{
|
|
return 0;
|
|
}
|
|
#elif defined(CONFIG_E200)
|
|
int machine_check_e200(struct pt_regs *regs)
|
|
{
|
|
unsigned long reason = get_mc_reason(regs);
|
|
|
|
printk("Machine check in kernel mode.\n");
|
|
printk("Caused by (from MCSR=%lx): ", reason);
|
|
|
|
if (reason & MCSR_MCP)
|
|
printk("Machine Check Signal\n");
|
|
if (reason & MCSR_CP_PERR)
|
|
printk("Cache Push Parity Error\n");
|
|
if (reason & MCSR_CPERR)
|
|
printk("Cache Parity Error\n");
|
|
if (reason & MCSR_EXCP_ERR)
|
|
printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
|
|
if (reason & MCSR_BUS_IRERR)
|
|
printk("Bus - Read Bus Error on instruction fetch\n");
|
|
if (reason & MCSR_BUS_DRERR)
|
|
printk("Bus - Read Bus Error on data load\n");
|
|
if (reason & MCSR_BUS_WRERR)
|
|
printk("Bus - Write Bus Error on buffered store or cache line push\n");
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
int machine_check_generic(struct pt_regs *regs)
|
|
{
|
|
unsigned long reason = get_mc_reason(regs);
|
|
|
|
printk("Machine check in kernel mode.\n");
|
|
printk("Caused by (from SRR1=%lx): ", reason);
|
|
switch (reason & 0x601F0000) {
|
|
case 0x80000:
|
|
printk("Machine check signal\n");
|
|
break;
|
|
case 0: /* for 601 */
|
|
case 0x40000:
|
|
case 0x140000: /* 7450 MSS error and TEA */
|
|
printk("Transfer error ack signal\n");
|
|
break;
|
|
case 0x20000:
|
|
printk("Data parity error signal\n");
|
|
break;
|
|
case 0x10000:
|
|
printk("Address parity error signal\n");
|
|
break;
|
|
case 0x20000000:
|
|
printk("L1 Data Cache error\n");
|
|
break;
|
|
case 0x40000000:
|
|
printk("L1 Instruction Cache error\n");
|
|
break;
|
|
case 0x00100000:
|
|
printk("L2 data cache parity error\n");
|
|
break;
|
|
default:
|
|
printk("Unknown values in msr\n");
|
|
}
|
|
return 0;
|
|
}
|
|
#endif /* everything else */
|
|
|
|
void machine_check_exception(struct pt_regs *regs)
|
|
{
|
|
int recover = 0;
|
|
|
|
__get_cpu_var(irq_stat).mce_exceptions++;
|
|
|
|
/* See if any machine dependent calls. In theory, we would want
|
|
* to call the CPU first, and call the ppc_md. one if the CPU
|
|
* one returns a positive number. However there is existing code
|
|
* that assumes the board gets a first chance, so let's keep it
|
|
* that way for now and fix things later. --BenH.
|
|
*/
|
|
if (ppc_md.machine_check_exception)
|
|
recover = ppc_md.machine_check_exception(regs);
|
|
else if (cur_cpu_spec->machine_check)
|
|
recover = cur_cpu_spec->machine_check(regs);
|
|
|
|
if (recover > 0)
|
|
return;
|
|
|
|
if (user_mode(regs)) {
|
|
regs->msr |= MSR_RI;
|
|
_exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
|
|
return;
|
|
}
|
|
|
|
#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
|
|
/* the qspan pci read routines can cause machine checks -- Cort
|
|
*
|
|
* yuck !!! that totally needs to go away ! There are better ways
|
|
* to deal with that than having a wart in the mcheck handler.
|
|
* -- BenH
|
|
*/
|
|
bad_page_fault(regs, regs->dar, SIGBUS);
|
|
return;
|
|
#endif
|
|
|
|
if (debugger_fault_handler(regs)) {
|
|
regs->msr |= MSR_RI;
|
|
return;
|
|
}
|
|
|
|
if (check_io_access(regs))
|
|
return;
|
|
|
|
if (debugger_fault_handler(regs))
|
|
return;
|
|
die("Machine check", regs, SIGBUS);
|
|
|
|
/* Must die if the interrupt is not recoverable */
|
|
if (!(regs->msr & MSR_RI))
|
|
panic("Unrecoverable Machine check");
|
|
}
|
|
|
|
void SMIException(struct pt_regs *regs)
|
|
{
|
|
die("System Management Interrupt", regs, SIGABRT);
|
|
}
|
|
|
|
void unknown_exception(struct pt_regs *regs)
|
|
{
|
|
printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
|
|
regs->nip, regs->msr, regs->trap);
|
|
|
|
_exception(SIGTRAP, regs, 0, 0);
|
|
}
|
|
|
|
void instruction_breakpoint_exception(struct pt_regs *regs)
|
|
{
|
|
if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
|
|
5, SIGTRAP) == NOTIFY_STOP)
|
|
return;
|
|
if (debugger_iabr_match(regs))
|
|
return;
|
|
_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
|
|
}
|
|
|
|
void RunModeException(struct pt_regs *regs)
|
|
{
|
|
_exception(SIGTRAP, regs, 0, 0);
|
|
}
|
|
|
|
void __kprobes single_step_exception(struct pt_regs *regs)
|
|
{
|
|
clear_single_step(regs);
|
|
|
|
if (notify_die(DIE_SSTEP, "single_step", regs, 5,
|
|
5, SIGTRAP) == NOTIFY_STOP)
|
|
return;
|
|
if (debugger_sstep(regs))
|
|
return;
|
|
|
|
_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
|
|
}
|
|
|
|
/*
|
|
* After we have successfully emulated an instruction, we have to
|
|
* check if the instruction was being single-stepped, and if so,
|
|
* pretend we got a single-step exception. This was pointed out
|
|
* by Kumar Gala. -- paulus
|
|
*/
|
|
static void emulate_single_step(struct pt_regs *regs)
|
|
{
|
|
if (single_stepping(regs))
|
|
single_step_exception(regs);
|
|
}
|
|
|
|
static inline int __parse_fpscr(unsigned long fpscr)
|
|
{
|
|
int ret = 0;
|
|
|
|
/* Invalid operation */
|
|
if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
|
|
ret = FPE_FLTINV;
|
|
|
|
/* Overflow */
|
|
else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
|
|
ret = FPE_FLTOVF;
|
|
|
|
/* Underflow */
|
|
else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
|
|
ret = FPE_FLTUND;
|
|
|
|
/* Divide by zero */
|
|
else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
|
|
ret = FPE_FLTDIV;
|
|
|
|
/* Inexact result */
|
|
else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
|
|
ret = FPE_FLTRES;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void parse_fpe(struct pt_regs *regs)
|
|
{
|
|
int code = 0;
|
|
|
|
flush_fp_to_thread(current);
|
|
|
|
code = __parse_fpscr(current->thread.fpscr.val);
|
|
|
|
_exception(SIGFPE, regs, code, regs->nip);
|
|
}
|
|
|
|
/*
|
|
* Illegal instruction emulation support. Originally written to
|
|
* provide the PVR to user applications using the mfspr rd, PVR.
|
|
* Return non-zero if we can't emulate, or -EFAULT if the associated
|
|
* memory access caused an access fault. Return zero on success.
|
|
*
|
|
* There are a couple of ways to do this, either "decode" the instruction
|
|
* or directly match lots of bits. In this case, matching lots of
|
|
* bits is faster and easier.
|
|
*
|
|
*/
|
|
static int emulate_string_inst(struct pt_regs *regs, u32 instword)
|
|
{
|
|
u8 rT = (instword >> 21) & 0x1f;
|
|
u8 rA = (instword >> 16) & 0x1f;
|
|
u8 NB_RB = (instword >> 11) & 0x1f;
|
|
u32 num_bytes;
|
|
unsigned long EA;
|
|
int pos = 0;
|
|
|
|
/* Early out if we are an invalid form of lswx */
|
|
if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
|
|
if ((rT == rA) || (rT == NB_RB))
|
|
return -EINVAL;
|
|
|
|
EA = (rA == 0) ? 0 : regs->gpr[rA];
|
|
|
|
switch (instword & PPC_INST_STRING_MASK) {
|
|
case PPC_INST_LSWX:
|
|
case PPC_INST_STSWX:
|
|
EA += NB_RB;
|
|
num_bytes = regs->xer & 0x7f;
|
|
break;
|
|
case PPC_INST_LSWI:
|
|
case PPC_INST_STSWI:
|
|
num_bytes = (NB_RB == 0) ? 32 : NB_RB;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
while (num_bytes != 0)
|
|
{
|
|
u8 val;
|
|
u32 shift = 8 * (3 - (pos & 0x3));
|
|
|
|
switch ((instword & PPC_INST_STRING_MASK)) {
|
|
case PPC_INST_LSWX:
|
|
case PPC_INST_LSWI:
|
|
if (get_user(val, (u8 __user *)EA))
|
|
return -EFAULT;
|
|
/* first time updating this reg,
|
|
* zero it out */
|
|
if (pos == 0)
|
|
regs->gpr[rT] = 0;
|
|
regs->gpr[rT] |= val << shift;
|
|
break;
|
|
case PPC_INST_STSWI:
|
|
case PPC_INST_STSWX:
|
|
val = regs->gpr[rT] >> shift;
|
|
if (put_user(val, (u8 __user *)EA))
|
|
return -EFAULT;
|
|
break;
|
|
}
|
|
/* move EA to next address */
|
|
EA += 1;
|
|
num_bytes--;
|
|
|
|
/* manage our position within the register */
|
|
if (++pos == 4) {
|
|
pos = 0;
|
|
if (++rT == 32)
|
|
rT = 0;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
|
|
{
|
|
u32 ra,rs;
|
|
unsigned long tmp;
|
|
|
|
ra = (instword >> 16) & 0x1f;
|
|
rs = (instword >> 21) & 0x1f;
|
|
|
|
tmp = regs->gpr[rs];
|
|
tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
|
|
tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
|
|
tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
|
|
regs->gpr[ra] = tmp;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int emulate_isel(struct pt_regs *regs, u32 instword)
|
|
{
|
|
u8 rT = (instword >> 21) & 0x1f;
|
|
u8 rA = (instword >> 16) & 0x1f;
|
|
u8 rB = (instword >> 11) & 0x1f;
|
|
u8 BC = (instword >> 6) & 0x1f;
|
|
u8 bit;
|
|
unsigned long tmp;
|
|
|
|
tmp = (rA == 0) ? 0 : regs->gpr[rA];
|
|
bit = (regs->ccr >> (31 - BC)) & 0x1;
|
|
|
|
regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int emulate_instruction(struct pt_regs *regs)
|
|
{
|
|
u32 instword;
|
|
u32 rd;
|
|
|
|
if (!user_mode(regs) || (regs->msr & MSR_LE))
|
|
return -EINVAL;
|
|
CHECK_FULL_REGS(regs);
|
|
|
|
if (get_user(instword, (u32 __user *)(regs->nip)))
|
|
return -EFAULT;
|
|
|
|
/* Emulate the mfspr rD, PVR. */
|
|
if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
|
|
PPC_WARN_EMULATED(mfpvr, regs);
|
|
rd = (instword >> 21) & 0x1f;
|
|
regs->gpr[rd] = mfspr(SPRN_PVR);
|
|
return 0;
|
|
}
|
|
|
|
/* Emulating the dcba insn is just a no-op. */
|
|
if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
|
|
PPC_WARN_EMULATED(dcba, regs);
|
|
return 0;
|
|
}
|
|
|
|
/* Emulate the mcrxr insn. */
|
|
if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
|
|
int shift = (instword >> 21) & 0x1c;
|
|
unsigned long msk = 0xf0000000UL >> shift;
|
|
|
|
PPC_WARN_EMULATED(mcrxr, regs);
|
|
regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
|
|
regs->xer &= ~0xf0000000UL;
|
|
return 0;
|
|
}
|
|
|
|
/* Emulate load/store string insn. */
|
|
if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
|
|
PPC_WARN_EMULATED(string, regs);
|
|
return emulate_string_inst(regs, instword);
|
|
}
|
|
|
|
/* Emulate the popcntb (Population Count Bytes) instruction. */
|
|
if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
|
|
PPC_WARN_EMULATED(popcntb, regs);
|
|
return emulate_popcntb_inst(regs, instword);
|
|
}
|
|
|
|
/* Emulate isel (Integer Select) instruction */
|
|
if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
|
|
PPC_WARN_EMULATED(isel, regs);
|
|
return emulate_isel(regs, instword);
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
int is_valid_bugaddr(unsigned long addr)
|
|
{
|
|
return is_kernel_addr(addr);
|
|
}
|
|
|
|
void __kprobes program_check_exception(struct pt_regs *regs)
|
|
{
|
|
unsigned int reason = get_reason(regs);
|
|
extern int do_mathemu(struct pt_regs *regs);
|
|
|
|
/* We can now get here via a FP Unavailable exception if the core
|
|
* has no FPU, in that case the reason flags will be 0 */
|
|
|
|
if (reason & REASON_FP) {
|
|
/* IEEE FP exception */
|
|
parse_fpe(regs);
|
|
return;
|
|
}
|
|
if (reason & REASON_TRAP) {
|
|
/* Debugger is first in line to stop recursive faults in
|
|
* rcu_lock, notify_die, or atomic_notifier_call_chain */
|
|
if (debugger_bpt(regs))
|
|
return;
|
|
|
|
/* trap exception */
|
|
if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
|
|
== NOTIFY_STOP)
|
|
return;
|
|
|
|
if (!(regs->msr & MSR_PR) && /* not user-mode */
|
|
report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
|
|
regs->nip += 4;
|
|
return;
|
|
}
|
|
_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
|
|
return;
|
|
}
|
|
|
|
local_irq_enable();
|
|
|
|
#ifdef CONFIG_MATH_EMULATION
|
|
/* (reason & REASON_ILLEGAL) would be the obvious thing here,
|
|
* but there seems to be a hardware bug on the 405GP (RevD)
|
|
* that means ESR is sometimes set incorrectly - either to
|
|
* ESR_DST (!?) or 0. In the process of chasing this with the
|
|
* hardware people - not sure if it can happen on any illegal
|
|
* instruction or only on FP instructions, whether there is a
|
|
* pattern to occurences etc. -dgibson 31/Mar/2003 */
|
|
switch (do_mathemu(regs)) {
|
|
case 0:
|
|
emulate_single_step(regs);
|
|
return;
|
|
case 1: {
|
|
int code = 0;
|
|
code = __parse_fpscr(current->thread.fpscr.val);
|
|
_exception(SIGFPE, regs, code, regs->nip);
|
|
return;
|
|
}
|
|
case -EFAULT:
|
|
_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
|
|
return;
|
|
}
|
|
/* fall through on any other errors */
|
|
#endif /* CONFIG_MATH_EMULATION */
|
|
|
|
/* Try to emulate it if we should. */
|
|
if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
|
|
switch (emulate_instruction(regs)) {
|
|
case 0:
|
|
regs->nip += 4;
|
|
emulate_single_step(regs);
|
|
return;
|
|
case -EFAULT:
|
|
_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (reason & REASON_PRIVILEGED)
|
|
_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
|
|
else
|
|
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
|
}
|
|
|
|
void alignment_exception(struct pt_regs *regs)
|
|
{
|
|
int sig, code, fixed = 0;
|
|
|
|
/* we don't implement logging of alignment exceptions */
|
|
if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
|
|
fixed = fix_alignment(regs);
|
|
|
|
if (fixed == 1) {
|
|
regs->nip += 4; /* skip over emulated instruction */
|
|
emulate_single_step(regs);
|
|
return;
|
|
}
|
|
|
|
/* Operand address was bad */
|
|
if (fixed == -EFAULT) {
|
|
sig = SIGSEGV;
|
|
code = SEGV_ACCERR;
|
|
} else {
|
|
sig = SIGBUS;
|
|
code = BUS_ADRALN;
|
|
}
|
|
if (user_mode(regs))
|
|
_exception(sig, regs, code, regs->dar);
|
|
else
|
|
bad_page_fault(regs, regs->dar, sig);
|
|
}
|
|
|
|
void StackOverflow(struct pt_regs *regs)
|
|
{
|
|
printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
|
|
current, regs->gpr[1]);
|
|
debugger(regs);
|
|
show_regs(regs);
|
|
panic("kernel stack overflow");
|
|
}
|
|
|
|
void nonrecoverable_exception(struct pt_regs *regs)
|
|
{
|
|
printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
|
|
regs->nip, regs->msr);
|
|
debugger(regs);
|
|
die("nonrecoverable exception", regs, SIGKILL);
|
|
}
|
|
|
|
void trace_syscall(struct pt_regs *regs)
|
|
{
|
|
printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
|
|
current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
|
|
regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
|
|
}
|
|
|
|
void kernel_fp_unavailable_exception(struct pt_regs *regs)
|
|
{
|
|
printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
|
|
"%lx at %lx\n", regs->trap, regs->nip);
|
|
die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
|
|
}
|
|
|
|
void altivec_unavailable_exception(struct pt_regs *regs)
|
|
{
|
|
if (user_mode(regs)) {
|
|
/* A user program has executed an altivec instruction,
|
|
but this kernel doesn't support altivec. */
|
|
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
|
return;
|
|
}
|
|
|
|
printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
|
|
"%lx at %lx\n", regs->trap, regs->nip);
|
|
die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
|
|
}
|
|
|
|
void vsx_unavailable_exception(struct pt_regs *regs)
|
|
{
|
|
if (user_mode(regs)) {
|
|
/* A user program has executed an vsx instruction,
|
|
but this kernel doesn't support vsx. */
|
|
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
|
return;
|
|
}
|
|
|
|
printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
|
|
"%lx at %lx\n", regs->trap, regs->nip);
|
|
die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
|
|
}
|
|
|
|
void performance_monitor_exception(struct pt_regs *regs)
|
|
{
|
|
__get_cpu_var(irq_stat).pmu_irqs++;
|
|
|
|
perf_irq(regs);
|
|
}
|
|
|
|
#ifdef CONFIG_8xx
|
|
void SoftwareEmulation(struct pt_regs *regs)
|
|
{
|
|
extern int do_mathemu(struct pt_regs *);
|
|
extern int Soft_emulate_8xx(struct pt_regs *);
|
|
#if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
|
|
int errcode;
|
|
#endif
|
|
|
|
CHECK_FULL_REGS(regs);
|
|
|
|
if (!user_mode(regs)) {
|
|
debugger(regs);
|
|
die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
|
|
}
|
|
|
|
#ifdef CONFIG_MATH_EMULATION
|
|
errcode = do_mathemu(regs);
|
|
if (errcode >= 0)
|
|
PPC_WARN_EMULATED(math, regs);
|
|
|
|
switch (errcode) {
|
|
case 0:
|
|
emulate_single_step(regs);
|
|
return;
|
|
case 1: {
|
|
int code = 0;
|
|
code = __parse_fpscr(current->thread.fpscr.val);
|
|
_exception(SIGFPE, regs, code, regs->nip);
|
|
return;
|
|
}
|
|
case -EFAULT:
|
|
_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
|
|
return;
|
|
default:
|
|
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
|
return;
|
|
}
|
|
|
|
#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
|
|
errcode = Soft_emulate_8xx(regs);
|
|
if (errcode >= 0)
|
|
PPC_WARN_EMULATED(8xx, regs);
|
|
|
|
switch (errcode) {
|
|
case 0:
|
|
emulate_single_step(regs);
|
|
return;
|
|
case 1:
|
|
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
|
return;
|
|
case -EFAULT:
|
|
_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
|
|
return;
|
|
}
|
|
#else
|
|
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
|
#endif
|
|
}
|
|
#endif /* CONFIG_8xx */
|
|
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
|
|
{
|
|
int changed = 0;
|
|
/*
|
|
* Determine the cause of the debug event, clear the
|
|
* event flags and send a trap to the handler. Torez
|
|
*/
|
|
if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
|
|
dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
|
current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
|
|
#endif
|
|
do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
|
|
5);
|
|
changed |= 0x01;
|
|
} else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
|
|
dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
|
|
do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
|
|
6);
|
|
changed |= 0x01;
|
|
} else if (debug_status & DBSR_IAC1) {
|
|
current->thread.dbcr0 &= ~DBCR0_IAC1;
|
|
dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
|
|
do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
|
|
1);
|
|
changed |= 0x01;
|
|
} else if (debug_status & DBSR_IAC2) {
|
|
current->thread.dbcr0 &= ~DBCR0_IAC2;
|
|
do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
|
|
2);
|
|
changed |= 0x01;
|
|
} else if (debug_status & DBSR_IAC3) {
|
|
current->thread.dbcr0 &= ~DBCR0_IAC3;
|
|
dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
|
|
do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
|
|
3);
|
|
changed |= 0x01;
|
|
} else if (debug_status & DBSR_IAC4) {
|
|
current->thread.dbcr0 &= ~DBCR0_IAC4;
|
|
do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
|
|
4);
|
|
changed |= 0x01;
|
|
}
|
|
/*
|
|
* At the point this routine was called, the MSR(DE) was turned off.
|
|
* Check all other debug flags and see if that bit needs to be turned
|
|
* back on or not.
|
|
*/
|
|
if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
|
|
regs->msr |= MSR_DE;
|
|
else
|
|
/* Make sure the IDM flag is off */
|
|
current->thread.dbcr0 &= ~DBCR0_IDM;
|
|
|
|
if (changed & 0x01)
|
|
mtspr(SPRN_DBCR0, current->thread.dbcr0);
|
|
}
|
|
|
|
void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
|
|
{
|
|
current->thread.dbsr = debug_status;
|
|
|
|
/* Hack alert: On BookE, Branch Taken stops on the branch itself, while
|
|
* on server, it stops on the target of the branch. In order to simulate
|
|
* the server behaviour, we thus restart right away with a single step
|
|
* instead of stopping here when hitting a BT
|
|
*/
|
|
if (debug_status & DBSR_BT) {
|
|
regs->msr &= ~MSR_DE;
|
|
|
|
/* Disable BT */
|
|
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
|
|
/* Clear the BT event */
|
|
mtspr(SPRN_DBSR, DBSR_BT);
|
|
|
|
/* Do the single step trick only when coming from userspace */
|
|
if (user_mode(regs)) {
|
|
current->thread.dbcr0 &= ~DBCR0_BT;
|
|
current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
|
|
regs->msr |= MSR_DE;
|
|
return;
|
|
}
|
|
|
|
if (notify_die(DIE_SSTEP, "block_step", regs, 5,
|
|
5, SIGTRAP) == NOTIFY_STOP) {
|
|
return;
|
|
}
|
|
if (debugger_sstep(regs))
|
|
return;
|
|
} else if (debug_status & DBSR_IC) { /* Instruction complete */
|
|
regs->msr &= ~MSR_DE;
|
|
|
|
/* Disable instruction completion */
|
|
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
|
|
/* Clear the instruction completion event */
|
|
mtspr(SPRN_DBSR, DBSR_IC);
|
|
|
|
if (notify_die(DIE_SSTEP, "single_step", regs, 5,
|
|
5, SIGTRAP) == NOTIFY_STOP) {
|
|
return;
|
|
}
|
|
|
|
if (debugger_sstep(regs))
|
|
return;
|
|
|
|
if (user_mode(regs)) {
|
|
current->thread.dbcr0 &= ~DBCR0_IC;
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
|
|
current->thread.dbcr1))
|
|
regs->msr |= MSR_DE;
|
|
else
|
|
/* Make sure the IDM bit is off */
|
|
current->thread.dbcr0 &= ~DBCR0_IDM;
|
|
#endif
|
|
}
|
|
|
|
_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
|
|
} else
|
|
handle_debug(regs, debug_status);
|
|
}
|
|
#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
|
|
|
|
#if !defined(CONFIG_TAU_INT)
|
|
void TAUException(struct pt_regs *regs)
|
|
{
|
|
printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
|
|
regs->nip, regs->msr, regs->trap, print_tainted());
|
|
}
|
|
#endif /* CONFIG_INT_TAU */
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
void altivec_assist_exception(struct pt_regs *regs)
|
|
{
|
|
int err;
|
|
|
|
if (!user_mode(regs)) {
|
|
printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
|
|
" at %lx\n", regs->nip);
|
|
die("Kernel VMX/Altivec assist exception", regs, SIGILL);
|
|
}
|
|
|
|
flush_altivec_to_thread(current);
|
|
|
|
PPC_WARN_EMULATED(altivec, regs);
|
|
err = emulate_altivec(regs);
|
|
if (err == 0) {
|
|
regs->nip += 4; /* skip emulated instruction */
|
|
emulate_single_step(regs);
|
|
return;
|
|
}
|
|
|
|
if (err == -EFAULT) {
|
|
/* got an error reading the instruction */
|
|
_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
|
|
} else {
|
|
/* didn't recognize the instruction */
|
|
/* XXX quick hack for now: set the non-Java bit in the VSCR */
|
|
if (printk_ratelimit())
|
|
printk(KERN_ERR "Unrecognized altivec instruction "
|
|
"in %s at %lx\n", current->comm, regs->nip);
|
|
current->thread.vscr.u[3] |= 0x10000;
|
|
}
|
|
}
|
|
#endif /* CONFIG_ALTIVEC */
|
|
|
|
#ifdef CONFIG_VSX
|
|
void vsx_assist_exception(struct pt_regs *regs)
|
|
{
|
|
if (!user_mode(regs)) {
|
|
printk(KERN_EMERG "VSX assist exception in kernel mode"
|
|
" at %lx\n", regs->nip);
|
|
die("Kernel VSX assist exception", regs, SIGILL);
|
|
}
|
|
|
|
flush_vsx_to_thread(current);
|
|
printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
|
|
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
|
}
|
|
#endif /* CONFIG_VSX */
|
|
|
|
#ifdef CONFIG_FSL_BOOKE
|
|
void CacheLockingException(struct pt_regs *regs, unsigned long address,
|
|
unsigned long error_code)
|
|
{
|
|
/* We treat cache locking instructions from the user
|
|
* as priv ops, in the future we could try to do
|
|
* something smarter
|
|
*/
|
|
if (error_code & (ESR_DLK|ESR_ILK))
|
|
_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
|
|
return;
|
|
}
|
|
#endif /* CONFIG_FSL_BOOKE */
|
|
|
|
#ifdef CONFIG_SPE
|
|
void SPEFloatingPointException(struct pt_regs *regs)
|
|
{
|
|
extern int do_spe_mathemu(struct pt_regs *regs);
|
|
unsigned long spefscr;
|
|
int fpexc_mode;
|
|
int code = 0;
|
|
int err;
|
|
|
|
preempt_disable();
|
|
if (regs->msr & MSR_SPE)
|
|
giveup_spe(current);
|
|
preempt_enable();
|
|
|
|
spefscr = current->thread.spefscr;
|
|
fpexc_mode = current->thread.fpexc_mode;
|
|
|
|
if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
|
|
code = FPE_FLTOVF;
|
|
}
|
|
else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
|
|
code = FPE_FLTUND;
|
|
}
|
|
else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
|
|
code = FPE_FLTDIV;
|
|
else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
|
|
code = FPE_FLTINV;
|
|
}
|
|
else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
|
|
code = FPE_FLTRES;
|
|
|
|
err = do_spe_mathemu(regs);
|
|
if (err == 0) {
|
|
regs->nip += 4; /* skip emulated instruction */
|
|
emulate_single_step(regs);
|
|
return;
|
|
}
|
|
|
|
if (err == -EFAULT) {
|
|
/* got an error reading the instruction */
|
|
_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
|
|
} else if (err == -EINVAL) {
|
|
/* didn't recognize the instruction */
|
|
printk(KERN_ERR "unrecognized spe instruction "
|
|
"in %s at %lx\n", current->comm, regs->nip);
|
|
} else {
|
|
_exception(SIGFPE, regs, code, regs->nip);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
void SPEFloatingPointRoundException(struct pt_regs *regs)
|
|
{
|
|
extern int speround_handler(struct pt_regs *regs);
|
|
int err;
|
|
|
|
preempt_disable();
|
|
if (regs->msr & MSR_SPE)
|
|
giveup_spe(current);
|
|
preempt_enable();
|
|
|
|
regs->nip -= 4;
|
|
err = speround_handler(regs);
|
|
if (err == 0) {
|
|
regs->nip += 4; /* skip emulated instruction */
|
|
emulate_single_step(regs);
|
|
return;
|
|
}
|
|
|
|
if (err == -EFAULT) {
|
|
/* got an error reading the instruction */
|
|
_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
|
|
} else if (err == -EINVAL) {
|
|
/* didn't recognize the instruction */
|
|
printk(KERN_ERR "unrecognized spe instruction "
|
|
"in %s at %lx\n", current->comm, regs->nip);
|
|
} else {
|
|
_exception(SIGFPE, regs, 0, regs->nip);
|
|
return;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* We enter here if we get an unrecoverable exception, that is, one
|
|
* that happened at a point where the RI (recoverable interrupt) bit
|
|
* in the MSR is 0. This indicates that SRR0/1 are live, and that
|
|
* we therefore lost state by taking this exception.
|
|
*/
|
|
void unrecoverable_exception(struct pt_regs *regs)
|
|
{
|
|
printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
|
|
regs->trap, regs->nip);
|
|
die("Unrecoverable exception", regs, SIGABRT);
|
|
}
|
|
|
|
#ifdef CONFIG_BOOKE_WDT
|
|
/*
|
|
* Default handler for a Watchdog exception,
|
|
* spins until a reboot occurs
|
|
*/
|
|
void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
|
|
{
|
|
/* Generic WatchdogHandler, implement your own */
|
|
mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
|
|
return;
|
|
}
|
|
|
|
void WatchdogException(struct pt_regs *regs)
|
|
{
|
|
printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
|
|
WatchdogHandler(regs);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* We enter here if we discover during exception entry that we are
|
|
* running in supervisor mode with a userspace value in the stack pointer.
|
|
*/
|
|
void kernel_bad_stack(struct pt_regs *regs)
|
|
{
|
|
printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
|
|
regs->gpr[1], regs->nip);
|
|
die("Bad kernel stack pointer", regs, SIGABRT);
|
|
}
|
|
|
|
void __init trap_init(void)
|
|
{
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_PPC_EMULATED_STATS
|
|
|
|
#define WARN_EMULATED_SETUP(type) .type = { .name = #type }
|
|
|
|
struct ppc_emulated ppc_emulated = {
|
|
#ifdef CONFIG_ALTIVEC
|
|
WARN_EMULATED_SETUP(altivec),
|
|
#endif
|
|
WARN_EMULATED_SETUP(dcba),
|
|
WARN_EMULATED_SETUP(dcbz),
|
|
WARN_EMULATED_SETUP(fp_pair),
|
|
WARN_EMULATED_SETUP(isel),
|
|
WARN_EMULATED_SETUP(mcrxr),
|
|
WARN_EMULATED_SETUP(mfpvr),
|
|
WARN_EMULATED_SETUP(multiple),
|
|
WARN_EMULATED_SETUP(popcntb),
|
|
WARN_EMULATED_SETUP(spe),
|
|
WARN_EMULATED_SETUP(string),
|
|
WARN_EMULATED_SETUP(unaligned),
|
|
#ifdef CONFIG_MATH_EMULATION
|
|
WARN_EMULATED_SETUP(math),
|
|
#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
|
|
WARN_EMULATED_SETUP(8xx),
|
|
#endif
|
|
#ifdef CONFIG_VSX
|
|
WARN_EMULATED_SETUP(vsx),
|
|
#endif
|
|
};
|
|
|
|
u32 ppc_warn_emulated;
|
|
|
|
void ppc_warn_emulated_print(const char *type)
|
|
{
|
|
if (printk_ratelimit())
|
|
pr_warning("%s used emulated %s instruction\n", current->comm,
|
|
type);
|
|
}
|
|
|
|
static int __init ppc_warn_emulated_init(void)
|
|
{
|
|
struct dentry *dir, *d;
|
|
unsigned int i;
|
|
struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
|
|
|
|
if (!powerpc_debugfs_root)
|
|
return -ENODEV;
|
|
|
|
dir = debugfs_create_dir("emulated_instructions",
|
|
powerpc_debugfs_root);
|
|
if (!dir)
|
|
return -ENOMEM;
|
|
|
|
d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
|
|
&ppc_warn_emulated);
|
|
if (!d)
|
|
goto fail;
|
|
|
|
for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
|
|
d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
|
|
(u32 *)&entries[i].val.counter);
|
|
if (!d)
|
|
goto fail;
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
debugfs_remove_recursive(dir);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
device_initcall(ppc_warn_emulated_init);
|
|
|
|
#endif /* CONFIG_PPC_EMULATED_STATS */
|