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36e5505dfb
After the device has signaled the end of reset by clearing the reset bit, it will automatically reinit MHI and the internal device structures. Once That is done, the device will signal it has entered the ready state. Signaling the ready state involves sending an interrupt (MSI) to the host which might cause IOMMU faults if it occurs at the wrong time. If the controller is being powered down, and possibly removed, then the reset flow would only wait for the end of reset. At which point, the host and device would start a race. The host may complete its reset work, and remove the interrupt handler, which would cause the interrupt to be disabled in the IOMMU. If that occurs before the device signals the ready state, then the IOMMU will fault since it blocked an interrupt. While harmless, the fault would appear like a serious issue has occurred so let's silence it by making sure the device hits the ready state before the host completes its reset processing. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Hemant Kumar <quic_hemantk@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1650302562-30964-1-git-send-email-quic_jhugo@quicinc.com Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
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| .. | ||
| fsl-mc | ||
| mhi | ||
| arm-cci.c | ||
| arm-integrator-lm.c | ||
| brcmstb_gisb.c | ||
| bt1-apb.c | ||
| bt1-axi.c | ||
| da8xx-mstpri.c | ||
| hisi_lpc.c | ||
| imx-weim.c | ||
| intel-ixp4xx-eb.c | ||
| Kconfig | ||
| Makefile | ||
| mips_cdmm.c | ||
| moxtet.c | ||
| mvebu-mbus.c | ||
| omap-ocp2scp.c | ||
| omap_l3_noc.c | ||
| omap_l3_noc.h | ||
| omap_l3_smx.c | ||
| omap_l3_smx.h | ||
| qcom-ebi2.c | ||
| simple-pm-bus.c | ||
| sun50i-de2.c | ||
| sunxi-rsb.c | ||
| tegra-aconnect.c | ||
| tegra-gmi.c | ||
| ti-pwmss.c | ||
| ti-sysc.c | ||
| ts-nbus.c | ||
| uniphier-system-bus.c | ||
| vexpress-config.c | ||