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bdc1dad299
The left overs of a moved interrupt are cleaned up once the interrupt is raised on the new target CPU. Keeping the vector valid on the original target CPU guarantees that there can't be an interrupt lost if the affinity change races with an concurrent interrupt from the device. This cleanup utilizes the lowest priority interrupt vector for this cleanup, which makes sure that in the unlikely case when the to be cleaned up interrupt is pending in the local APICs IRR the cleanup vector does not live lock. But there is no real reason to use an interrupt vector for cleaning up the leftovers of a moved interrupt. It's not a high performance operation. The only requirement is that it happens on the original target CPU. Convert it to use a timer instead and adjust the code accordingly. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Xin Li <xin3.li@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20230621171248.6805-3-xin3.li@intel.com
142 lines
4 KiB
C
142 lines
4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_IRQ_VECTORS_H
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#define _ASM_X86_IRQ_VECTORS_H
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#include <linux/threads.h>
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/*
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* Linux IRQ vector layout.
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*
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* There are 256 IDT entries (per CPU - each entry is 8 bytes) which can
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* be defined by Linux. They are used as a jump table by the CPU when a
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* given vector is triggered - by a CPU-external, CPU-internal or
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* software-triggered event.
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*
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* Linux sets the kernel code address each entry jumps to early during
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* bootup, and never changes them. This is the general layout of the
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* IDT entries:
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*
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* Vectors 0 ... 31 : system traps and exceptions - hardcoded events
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* Vectors 32 ... 127 : device interrupts
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* Vector 128 : legacy int80 syscall interface
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* Vectors 129 ... LOCAL_TIMER_VECTOR-1
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* Vectors LOCAL_TIMER_VECTOR ... 255 : special interrupts
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*
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* 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
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*
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* This file enumerates the exact layout of them:
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*/
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/* This is used as an interrupt vector when programming the APIC. */
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#define NMI_VECTOR 0x02
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/*
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* IDT vectors usable for external interrupt sources start at 0x20.
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* (0x80 is the syscall vector, 0x30-0x3f are for ISA)
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*/
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#define FIRST_EXTERNAL_VECTOR 0x20
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#define IA32_SYSCALL_VECTOR 0x80
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/*
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* Vectors 0x30-0x3f are used for ISA interrupts.
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* round up to the next 16-vector boundary
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*/
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#define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq)
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/*
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* Special IRQ vectors used by the SMP architecture, 0xf0-0xff
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*
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* some of the following vectors are 'rare', they are merged
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* into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
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* TLB, reschedule and local APIC vectors are performance-critical.
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*/
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#define SPURIOUS_APIC_VECTOR 0xff
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/*
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* Sanity check
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*/
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#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
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# error SPURIOUS_APIC_VECTOR definition error
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#endif
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#define ERROR_APIC_VECTOR 0xfe
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#define RESCHEDULE_VECTOR 0xfd
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#define CALL_FUNCTION_VECTOR 0xfc
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#define CALL_FUNCTION_SINGLE_VECTOR 0xfb
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#define THERMAL_APIC_VECTOR 0xfa
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#define THRESHOLD_APIC_VECTOR 0xf9
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#define REBOOT_VECTOR 0xf8
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/*
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* Generic system vector for platform specific use
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*/
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#define X86_PLATFORM_IPI_VECTOR 0xf7
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/*
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* IRQ work vector:
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*/
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#define IRQ_WORK_VECTOR 0xf6
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/* 0xf5 - unused, was UV_BAU_MESSAGE */
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#define DEFERRED_ERROR_VECTOR 0xf4
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/* Vector on which hypervisor callbacks will be delivered */
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#define HYPERVISOR_CALLBACK_VECTOR 0xf3
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/* Vector for KVM to deliver posted interrupt IPI */
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#ifdef CONFIG_HAVE_KVM
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#define POSTED_INTR_VECTOR 0xf2
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#define POSTED_INTR_WAKEUP_VECTOR 0xf1
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#define POSTED_INTR_NESTED_VECTOR 0xf0
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#endif
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#define MANAGED_IRQ_SHUTDOWN_VECTOR 0xef
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#if IS_ENABLED(CONFIG_HYPERV)
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#define HYPERV_REENLIGHTENMENT_VECTOR 0xee
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#define HYPERV_STIMER0_VECTOR 0xed
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#endif
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#define LOCAL_TIMER_VECTOR 0xec
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#define NR_VECTORS 256
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#ifdef CONFIG_X86_LOCAL_APIC
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#define FIRST_SYSTEM_VECTOR LOCAL_TIMER_VECTOR
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#else
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#define FIRST_SYSTEM_VECTOR NR_VECTORS
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#endif
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#define NR_EXTERNAL_VECTORS (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
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#define NR_SYSTEM_VECTORS (NR_VECTORS - FIRST_SYSTEM_VECTOR)
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/*
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* Size the maximum number of interrupts.
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*
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* If the irq_desc[] array has a sparse layout, we can size things
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* generously - it scales up linearly with the maximum number of CPUs,
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* and the maximum number of IO-APICs, whichever is higher.
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*
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* In other cases we size more conservatively, to not create too large
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* static arrays.
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*/
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#define NR_IRQS_LEGACY 16
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#define CPU_VECTOR_LIMIT (64 * NR_CPUS)
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#define IO_APIC_VECTOR_LIMIT (32 * MAX_IO_APICS)
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#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_PCI_MSI)
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#define NR_IRQS \
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(CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \
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(NR_VECTORS + CPU_VECTOR_LIMIT) : \
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(NR_VECTORS + IO_APIC_VECTOR_LIMIT))
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#elif defined(CONFIG_X86_IO_APIC)
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#define NR_IRQS (NR_VECTORS + IO_APIC_VECTOR_LIMIT)
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#elif defined(CONFIG_PCI_MSI)
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#define NR_IRQS (NR_VECTORS + CPU_VECTOR_LIMIT)
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#else
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#define NR_IRQS NR_IRQS_LEGACY
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#endif
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#endif /* _ASM_X86_IRQ_VECTORS_H */
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