Icenowy Zheng 8eb8fe67e2 riscv: errata: fix T-Head dcache.cva encoding ... The dcache.cva encoding shown in the comments are wrong, it's for dcache.cval1 (which is restricted to L1) instead. Fix this in the comment and in the hardcoded instruction. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Guo Ren <guoren@kernel.org> Tested-by: Drew Fustini <dfustini@baylibre.com> Link: https://lore.kernel.org/r/20230912072410.2481-1-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2023-09-12 13:58:40 -07:00
..
asm	riscv: errata: fix T-Head dcache.cva encoding	2023-09-12 13:58:40 -07:00
uapi/asm	RISC-V Patches for the 6.6 Merge Window, Part 2 (try 2)	2023-09-09 14:25:11 -07:00