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874e2cc189
Implement primitives necessary for the 4th level folding, add walks of p4d level where appropriate and remove usage of __ARCH_USE_5LEVEL_HACK. Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Brian Cain <bcain@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christophe Leroy <christophe.leroy@c-s.fr> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: James Morse <james.morse@arm.com> Cc: Jonas Bonn <jonas@southpole.se> Cc: Julien Thierry <julien.thierry.kdev@gmail.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Paul Mackerras <paulus@samba.org> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/20200414153455.21744-12-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
82 lines
2 KiB
C
82 lines
2 KiB
C
/*
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* TLB miss handler for SH with an MMU.
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2003 - 2012 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/kprobes.h>
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#include <linux/kdebug.h>
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#include <asm/mmu_context.h>
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#include <asm/thread_info.h>
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/*
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* Called with interrupts disabled.
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*/
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asmlinkage int __kprobes
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handle_tlbmiss(struct pt_regs *regs, unsigned long error_code,
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unsigned long address)
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{
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pgd_t *pgd;
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p4d_t *p4d;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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pte_t entry;
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/*
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* We don't take page faults for P1, P2, and parts of P4, these
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* are always mapped, whether it be due to legacy behaviour in
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* 29-bit mode, or due to PMB configuration in 32-bit mode.
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*/
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if (address >= P3SEG && address < P3_ADDR_MAX) {
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pgd = pgd_offset_k(address);
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} else {
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if (unlikely(address >= TASK_SIZE || !current->mm))
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return 1;
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pgd = pgd_offset(current->mm, address);
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}
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p4d = p4d_offset(pgd, address);
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if (p4d_none_or_clear_bad(p4d))
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return 1;
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pud = pud_offset(p4d, address);
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if (pud_none_or_clear_bad(pud))
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return 1;
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pmd = pmd_offset(pud, address);
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if (pmd_none_or_clear_bad(pmd))
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return 1;
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pte = pte_offset_kernel(pmd, address);
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entry = *pte;
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if (unlikely(pte_none(entry) || pte_not_present(entry)))
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return 1;
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if (unlikely(error_code && !pte_write(entry)))
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return 1;
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if (error_code)
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entry = pte_mkdirty(entry);
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entry = pte_mkyoung(entry);
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set_pte(pte, entry);
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#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SMP)
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/*
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* SH-4 does not set MMUCR.RC to the corresponding TLB entry in
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* the case of an initial page write exception, so we need to
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* flush it in order to avoid potential TLB entry duplication.
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*/
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if (error_code == FAULT_CODE_INITIAL)
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local_flush_tlb_one(get_asid(), address & PAGE_MASK);
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#endif
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set_thread_fault_code(error_code);
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update_mmu_cache(NULL, address, pte);
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return 0;
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}
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