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007faec014
Hyper-V needs to issue the GHCB HV call in order to read/write MSRs in
Isolation VMs. For that, expose sev_es_ghcb_hv_call().
The Hyper-V Isolation VMs are unenlightened guests and run a paravisor
at VMPL0 for communicating. GHCB pages are being allocated and set up
by that paravisor. Linux gets the GHCB page's physical address via
MSR_AMD64_SEV_ES_GHCB from the paravisor and should not change it.
Add a @set_ghcb_msr parameter to sev_es_ghcb_hv_call() to control
whether the function should set the GHCB's address prior to the call or
not and export that function for use by HyperV.
[ bp: - Massage commit message
- add a struct ghcb forward declaration to fix randconfig builds. ]
Signed-off-by: Tianyu Lan <Tianyu.Lan@microsoft.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/20211025122116.264793-6-ltykernel@gmail.com
98 lines
2.6 KiB
C
98 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* AMD Encrypted Register State Support
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*
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* Author: Joerg Roedel <jroedel@suse.de>
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*/
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#ifndef __ASM_ENCRYPTED_STATE_H
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#define __ASM_ENCRYPTED_STATE_H
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#include <linux/types.h>
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#include <asm/insn.h>
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#include <asm/sev-common.h>
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#define GHCB_PROTO_OUR 0x0001UL
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#define GHCB_PROTOCOL_MAX 1ULL
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#define GHCB_DEFAULT_USAGE 0ULL
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#define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); }
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enum es_result {
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ES_OK, /* All good */
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ES_UNSUPPORTED, /* Requested operation not supported */
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ES_VMM_ERROR, /* Unexpected state from the VMM */
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ES_DECODE_FAILED, /* Instruction decoding failed */
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ES_EXCEPTION, /* Instruction caused exception */
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ES_RETRY, /* Retry instruction emulation */
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};
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struct es_fault_info {
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unsigned long vector;
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unsigned long error_code;
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unsigned long cr2;
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};
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struct pt_regs;
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/* ES instruction emulation context */
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struct es_em_ctxt {
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struct pt_regs *regs;
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struct insn insn;
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struct es_fault_info fi;
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};
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void do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code);
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static inline u64 lower_bits(u64 val, unsigned int bits)
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{
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u64 mask = (1ULL << bits) - 1;
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return (val & mask);
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}
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struct real_mode_header;
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enum stack_type;
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struct ghcb;
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/* Early IDT entry points for #VC handler */
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extern void vc_no_ghcb(void);
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extern void vc_boot_ghcb(void);
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extern bool handle_vc_boot_ghcb(struct pt_regs *regs);
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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extern struct static_key_false sev_es_enable_key;
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extern void __sev_es_ist_enter(struct pt_regs *regs);
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extern void __sev_es_ist_exit(void);
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static __always_inline void sev_es_ist_enter(struct pt_regs *regs)
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{
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if (static_branch_unlikely(&sev_es_enable_key))
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__sev_es_ist_enter(regs);
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}
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static __always_inline void sev_es_ist_exit(void)
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{
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if (static_branch_unlikely(&sev_es_enable_key))
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__sev_es_ist_exit();
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}
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extern int sev_es_setup_ap_jump_table(struct real_mode_header *rmh);
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extern void __sev_es_nmi_complete(void);
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static __always_inline void sev_es_nmi_complete(void)
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{
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if (static_branch_unlikely(&sev_es_enable_key))
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__sev_es_nmi_complete();
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}
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extern int __init sev_es_efi_map_ghcbs(pgd_t *pgd);
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extern enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb,
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bool set_ghcb_msr,
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struct es_em_ctxt *ctxt,
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u64 exit_code, u64 exit_info_1,
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u64 exit_info_2);
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#else
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static inline void sev_es_ist_enter(struct pt_regs *regs) { }
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static inline void sev_es_ist_exit(void) { }
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static inline int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { return 0; }
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static inline void sev_es_nmi_complete(void) { }
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static inline int sev_es_efi_map_ghcbs(pgd_t *pgd) { return 0; }
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#endif
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#endif
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