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3c53f5e217
Certain devices can have GDSCs' which support ON as the only state. They can't be power collapsed to either hit RET or OFF. The clients drivers for these GDSCs' however would expect the state of the core to be reset following a GDSC disable and re-enable. To do this assert/deassert reset lines every time the client driver would request the GDSC to be powered on/off instead. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
237 lines
5.4 KiB
C
237 lines
5.4 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/pm_domain.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include "gdsc.h"
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#define PWR_ON_MASK BIT(31)
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#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
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#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
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#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
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#define SW_OVERRIDE_MASK BIT(2)
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#define HW_CONTROL_MASK BIT(1)
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#define SW_COLLAPSE_MASK BIT(0)
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/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
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#define EN_REST_WAIT_VAL (0x2 << 20)
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#define EN_FEW_WAIT_VAL (0x8 << 16)
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#define CLK_DIS_WAIT_VAL (0x2 << 12)
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#define RETAIN_MEM BIT(14)
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#define RETAIN_PERIPH BIT(13)
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#define TIMEOUT_US 100
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#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
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static int gdsc_is_enabled(struct gdsc *sc)
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{
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u32 val;
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int ret;
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ret = regmap_read(sc->regmap, sc->gdscr, &val);
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if (ret)
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return ret;
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return !!(val & PWR_ON_MASK);
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}
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static int gdsc_toggle_logic(struct gdsc *sc, bool en)
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{
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int ret;
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u32 val = en ? 0 : SW_COLLAPSE_MASK;
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u32 check = en ? PWR_ON_MASK : 0;
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unsigned long timeout;
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ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
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if (ret)
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return ret;
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timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
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do {
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ret = regmap_read(sc->regmap, sc->gdscr, &val);
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if (ret)
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return ret;
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if ((val & PWR_ON_MASK) == check)
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return 0;
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} while (time_before(jiffies, timeout));
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ret = regmap_read(sc->regmap, sc->gdscr, &val);
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if (ret)
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return ret;
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if ((val & PWR_ON_MASK) == check)
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return 0;
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return -ETIMEDOUT;
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}
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static inline int gdsc_deassert_reset(struct gdsc *sc)
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{
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int i;
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for (i = 0; i < sc->reset_count; i++)
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sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
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return 0;
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}
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static inline int gdsc_assert_reset(struct gdsc *sc)
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{
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int i;
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for (i = 0; i < sc->reset_count; i++)
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sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
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return 0;
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}
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static inline void gdsc_force_mem_on(struct gdsc *sc)
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{
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int i;
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u32 mask = RETAIN_MEM | RETAIN_PERIPH;
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for (i = 0; i < sc->cxc_count; i++)
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regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
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}
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static inline void gdsc_clear_mem_on(struct gdsc *sc)
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{
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int i;
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u32 mask = RETAIN_MEM | RETAIN_PERIPH;
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for (i = 0; i < sc->cxc_count; i++)
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regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
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}
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static int gdsc_enable(struct generic_pm_domain *domain)
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{
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struct gdsc *sc = domain_to_gdsc(domain);
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int ret;
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if (sc->pwrsts == PWRSTS_ON)
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return gdsc_deassert_reset(sc);
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ret = gdsc_toggle_logic(sc, true);
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if (ret)
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return ret;
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if (sc->pwrsts & PWRSTS_OFF)
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gdsc_force_mem_on(sc);
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/*
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* If clocks to this power domain were already on, they will take an
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* additional 4 clock cycles to re-enable after the power domain is
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* enabled. Delay to account for this. A delay is also needed to ensure
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* clocks are not enabled within 400ns of enabling power to the
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* memories.
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*/
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udelay(1);
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return 0;
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}
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static int gdsc_disable(struct generic_pm_domain *domain)
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{
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struct gdsc *sc = domain_to_gdsc(domain);
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if (sc->pwrsts == PWRSTS_ON)
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return gdsc_assert_reset(sc);
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if (sc->pwrsts & PWRSTS_OFF)
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gdsc_clear_mem_on(sc);
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return gdsc_toggle_logic(sc, false);
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}
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static int gdsc_init(struct gdsc *sc)
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{
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u32 mask, val;
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int on, ret;
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/*
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* Disable HW trigger: collapse/restore occur based on registers writes.
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* Disable SW override: Use hardware state-machine for sequencing.
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* Configure wait time between states.
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*/
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mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
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EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
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val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
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ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
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if (ret)
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return ret;
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/* Force gdsc ON if only ON state is supported */
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if (sc->pwrsts == PWRSTS_ON) {
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ret = gdsc_toggle_logic(sc, true);
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if (ret)
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return ret;
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}
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on = gdsc_is_enabled(sc);
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if (on < 0)
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return on;
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if (on || (sc->pwrsts & PWRSTS_RET))
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gdsc_force_mem_on(sc);
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else
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gdsc_clear_mem_on(sc);
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sc->pd.power_off = gdsc_disable;
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sc->pd.power_on = gdsc_enable;
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pm_genpd_init(&sc->pd, NULL, !on);
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return 0;
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}
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int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
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struct reset_controller_dev *rcdev, struct regmap *regmap)
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{
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int i, ret;
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struct genpd_onecell_data *data;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
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GFP_KERNEL);
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if (!data->domains)
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return -ENOMEM;
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data->num_domains = num;
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for (i = 0; i < num; i++) {
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if (!scs[i])
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continue;
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scs[i]->regmap = regmap;
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scs[i]->rcdev = rcdev;
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ret = gdsc_init(scs[i]);
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if (ret)
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return ret;
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data->domains[i] = &scs[i]->pd;
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}
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return of_genpd_add_provider_onecell(dev->of_node, data);
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}
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void gdsc_unregister(struct device *dev)
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{
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of_genpd_del_provider(dev->of_node);
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}
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