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1ca13de267
The device has a 64 bit clock register, where each clock tick is 16 nanoseconds, and so with this patch the driver is ready for the year 2038. Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
343 lines
7.4 KiB
C
343 lines
7.4 KiB
C
/*
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* PTP 1588 clock using the IXP46X
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*
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* Copyright (C) 2010 OMICRON electronics GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/ptp_clock_kernel.h>
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#include <mach/ixp46x_ts.h>
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#define DRIVER "ptp_ixp46x"
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#define N_EXT_TS 2
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#define MASTER_GPIO 8
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#define MASTER_IRQ 25
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#define SLAVE_GPIO 7
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#define SLAVE_IRQ 24
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struct ixp_clock {
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struct ixp46x_ts_regs *regs;
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struct ptp_clock *ptp_clock;
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struct ptp_clock_info caps;
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int exts0_enabled;
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int exts1_enabled;
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};
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DEFINE_SPINLOCK(register_lock);
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/*
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* Register access functions
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*/
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static u64 ixp_systime_read(struct ixp46x_ts_regs *regs)
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{
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u64 ns;
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u32 lo, hi;
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lo = __raw_readl(®s->systime_lo);
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hi = __raw_readl(®s->systime_hi);
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ns = ((u64) hi) << 32;
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ns |= lo;
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ns <<= TICKS_NS_SHIFT;
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return ns;
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}
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static void ixp_systime_write(struct ixp46x_ts_regs *regs, u64 ns)
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{
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u32 hi, lo;
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ns >>= TICKS_NS_SHIFT;
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hi = ns >> 32;
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lo = ns & 0xffffffff;
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__raw_writel(lo, ®s->systime_lo);
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__raw_writel(hi, ®s->systime_hi);
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}
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/*
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* Interrupt service routine
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*/
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static irqreturn_t isr(int irq, void *priv)
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{
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struct ixp_clock *ixp_clock = priv;
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struct ixp46x_ts_regs *regs = ixp_clock->regs;
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struct ptp_clock_event event;
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u32 ack = 0, lo, hi, val;
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val = __raw_readl(®s->event);
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if (val & TSER_SNS) {
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ack |= TSER_SNS;
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if (ixp_clock->exts0_enabled) {
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hi = __raw_readl(®s->asms_hi);
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lo = __raw_readl(®s->asms_lo);
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event.type = PTP_CLOCK_EXTTS;
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event.index = 0;
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event.timestamp = ((u64) hi) << 32;
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event.timestamp |= lo;
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event.timestamp <<= TICKS_NS_SHIFT;
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ptp_clock_event(ixp_clock->ptp_clock, &event);
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}
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}
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if (val & TSER_SNM) {
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ack |= TSER_SNM;
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if (ixp_clock->exts1_enabled) {
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hi = __raw_readl(®s->amms_hi);
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lo = __raw_readl(®s->amms_lo);
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event.type = PTP_CLOCK_EXTTS;
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event.index = 1;
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event.timestamp = ((u64) hi) << 32;
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event.timestamp |= lo;
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event.timestamp <<= TICKS_NS_SHIFT;
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ptp_clock_event(ixp_clock->ptp_clock, &event);
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}
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}
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if (val & TTIPEND)
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ack |= TTIPEND; /* this bit seems to be always set */
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if (ack) {
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__raw_writel(ack, ®s->event);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE;
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}
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/*
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* PTP clock operations
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*/
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static int ptp_ixp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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{
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u64 adj;
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u32 diff, addend;
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int neg_adj = 0;
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struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
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struct ixp46x_ts_regs *regs = ixp_clock->regs;
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if (ppb < 0) {
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neg_adj = 1;
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ppb = -ppb;
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}
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addend = DEFAULT_ADDEND;
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adj = addend;
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adj *= ppb;
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diff = div_u64(adj, 1000000000ULL);
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addend = neg_adj ? addend - diff : addend + diff;
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__raw_writel(addend, ®s->addend);
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return 0;
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}
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static int ptp_ixp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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s64 now;
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unsigned long flags;
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struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
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struct ixp46x_ts_regs *regs = ixp_clock->regs;
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spin_lock_irqsave(®ister_lock, flags);
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now = ixp_systime_read(regs);
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now += delta;
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ixp_systime_write(regs, now);
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spin_unlock_irqrestore(®ister_lock, flags);
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return 0;
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}
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static int ptp_ixp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
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{
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u64 ns;
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u32 remainder;
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unsigned long flags;
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struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
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struct ixp46x_ts_regs *regs = ixp_clock->regs;
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spin_lock_irqsave(®ister_lock, flags);
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ns = ixp_systime_read(regs);
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spin_unlock_irqrestore(®ister_lock, flags);
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ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
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ts->tv_nsec = remainder;
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return 0;
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}
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static int ptp_ixp_settime(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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u64 ns;
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unsigned long flags;
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struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
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struct ixp46x_ts_regs *regs = ixp_clock->regs;
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ns = ts->tv_sec * 1000000000ULL;
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ns += ts->tv_nsec;
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spin_lock_irqsave(®ister_lock, flags);
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ixp_systime_write(regs, ns);
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spin_unlock_irqrestore(®ister_lock, flags);
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return 0;
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}
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static int ptp_ixp_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on)
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{
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struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
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switch (rq->type) {
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case PTP_CLK_REQ_EXTTS:
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switch (rq->extts.index) {
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case 0:
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ixp_clock->exts0_enabled = on ? 1 : 0;
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break;
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case 1:
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ixp_clock->exts1_enabled = on ? 1 : 0;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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default:
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break;
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}
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return -EOPNOTSUPP;
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}
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static struct ptp_clock_info ptp_ixp_caps = {
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.owner = THIS_MODULE,
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.name = "IXP46X timer",
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.max_adj = 66666655,
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.n_ext_ts = N_EXT_TS,
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.n_pins = 0,
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.pps = 0,
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.adjfreq = ptp_ixp_adjfreq,
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.adjtime = ptp_ixp_adjtime,
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.gettime64 = ptp_ixp_gettime,
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.settime64 = ptp_ixp_settime,
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.enable = ptp_ixp_enable,
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};
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/* module operations */
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static struct ixp_clock ixp_clock;
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static int setup_interrupt(int gpio)
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{
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int irq;
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int err;
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err = gpio_request(gpio, "ixp4-ptp");
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if (err)
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return err;
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err = gpio_direction_input(gpio);
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if (err)
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return err;
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irq = gpio_to_irq(gpio);
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if (NO_IRQ == irq)
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return NO_IRQ;
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if (irq_set_irq_type(irq, IRQF_TRIGGER_FALLING)) {
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pr_err("cannot set trigger type for irq %d\n", irq);
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return NO_IRQ;
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}
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if (request_irq(irq, isr, 0, DRIVER, &ixp_clock)) {
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pr_err("request_irq failed for irq %d\n", irq);
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return NO_IRQ;
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}
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return irq;
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}
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static void __exit ptp_ixp_exit(void)
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{
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free_irq(MASTER_IRQ, &ixp_clock);
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free_irq(SLAVE_IRQ, &ixp_clock);
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ixp46x_phc_index = -1;
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ptp_clock_unregister(ixp_clock.ptp_clock);
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}
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static int __init ptp_ixp_init(void)
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{
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if (!cpu_is_ixp46x())
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return -ENODEV;
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ixp_clock.regs =
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(struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
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ixp_clock.caps = ptp_ixp_caps;
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ixp_clock.ptp_clock = ptp_clock_register(&ixp_clock.caps, NULL);
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if (IS_ERR(ixp_clock.ptp_clock))
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return PTR_ERR(ixp_clock.ptp_clock);
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ixp46x_phc_index = ptp_clock_index(ixp_clock.ptp_clock);
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__raw_writel(DEFAULT_ADDEND, &ixp_clock.regs->addend);
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__raw_writel(1, &ixp_clock.regs->trgt_lo);
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__raw_writel(0, &ixp_clock.regs->trgt_hi);
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__raw_writel(TTIPEND, &ixp_clock.regs->event);
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if (MASTER_IRQ != setup_interrupt(MASTER_GPIO)) {
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pr_err("failed to setup gpio %d as irq\n", MASTER_GPIO);
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goto no_master;
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}
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if (SLAVE_IRQ != setup_interrupt(SLAVE_GPIO)) {
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pr_err("failed to setup gpio %d as irq\n", SLAVE_GPIO);
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goto no_slave;
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}
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return 0;
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no_slave:
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free_irq(MASTER_IRQ, &ixp_clock);
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no_master:
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ptp_clock_unregister(ixp_clock.ptp_clock);
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return -ENODEV;
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}
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module_init(ptp_ixp_init);
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module_exit(ptp_ixp_exit);
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MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
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MODULE_DESCRIPTION("PTP clock using the IXP46X timer");
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MODULE_LICENSE("GPL");
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