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eb982001db
This patch moves the ti-soc-thermal driver out of the staging tree to the thermal tree. Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Zhang Rui <rui.zhang@intel.com> Cc: Eduardo Valentin <eduardo.valentin@ti.com> Cc: J Keerthy <j-keerthy@ti.com> Cc: Radhesh Fadnis <radhesh.fadnis@ti.com> Cc: Cyril Roelandt <tipecaml@gmail.com> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devel@driverdev.osuosl.org Cc: linux-pm@vger.kernel.org Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
200 lines
6.9 KiB
C
200 lines
6.9 KiB
C
/*
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* OMAP5xxx bandgap registers, bitfields and temperature definitions
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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* Contact:
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* Eduardo Valentin <eduardo.valentin@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __OMAP5XXX_BANDGAP_H
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#define __OMAP5XXX_BANDGAP_H
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/**
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* *** OMAP5430 ***
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*
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* Below, in sequence, are the Register definitions,
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* the bitfields and the temperature definitions for OMAP5430.
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*/
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/**
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* OMAP5430 register definitions
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*
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* Registers are defined as offsets. The offsets are
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* relative to FUSE_OPP_BGAP_GPU on 5430.
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*
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* Register below are grouped by domain (not necessarily in offset order)
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*/
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/* OMAP5430.GPU register offsets */
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#define OMAP5430_FUSE_OPP_BGAP_GPU 0x0
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#define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150
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#define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8
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#define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4
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#define OMAP5430_BGAP_CUMUL_DTEMP_GPU_OFFSET 0x1C0
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#define OMAP5430_BGAP_DTEMP_GPU_0_OFFSET 0x1F4
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#define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8
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#define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC
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#define OMAP5430_BGAP_DTEMP_GPU_3_OFFSET 0x200
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#define OMAP5430_BGAP_DTEMP_GPU_4_OFFSET 0x204
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/* OMAP5430.MPU register offsets */
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#define OMAP5430_FUSE_OPP_BGAP_MPU 0x4
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#define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C
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#define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4
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#define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0
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#define OMAP5430_BGAP_CUMUL_DTEMP_MPU_OFFSET 0x1BC
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#define OMAP5430_BGAP_DTEMP_MPU_0_OFFSET 0x1E0
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#define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E4
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#define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E8
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#define OMAP5430_BGAP_DTEMP_MPU_3_OFFSET 0x1EC
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#define OMAP5430_BGAP_DTEMP_MPU_4_OFFSET 0x1F0
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/* OMAP5430.MPU register offsets */
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#define OMAP5430_FUSE_OPP_BGAP_CORE 0x8
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#define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x154
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#define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC
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#define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B8
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#define OMAP5430_BGAP_CUMUL_DTEMP_CORE_OFFSET 0x1C4
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#define OMAP5430_BGAP_DTEMP_CORE_0_OFFSET 0x208
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#define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C
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#define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x210
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#define OMAP5430_BGAP_DTEMP_CORE_3_OFFSET 0x214
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#define OMAP5430_BGAP_DTEMP_CORE_4_OFFSET 0x218
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/* OMAP5430.common register offsets */
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#define OMAP5430_BGAP_CTRL_OFFSET 0x1A0
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#define OMAP5430_BGAP_STATUS_OFFSET 0x1C8
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/**
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* Register bitfields for OMAP5430
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*
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* All the macros bellow define the required bits for
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* controlling temperature on OMAP5430. Bit defines are
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* grouped by register.
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*/
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/* OMAP5430.TEMP_SENSOR */
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#define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK BIT(12)
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#define OMAP5430_BGAP_TEMPSOFF_MASK BIT(11)
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#define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)
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#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
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/* OMAP5430.BANDGAP_CTRL */
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#define OMAP5430_MASK_SIDLEMODE_MASK (0x3 << 30)
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#define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27)
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#define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23)
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#define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22)
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#define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21)
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#define OMAP5430_MASK_CLEAR_CORE_MASK BIT(20)
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#define OMAP5430_MASK_CLEAR_GPU_MASK BIT(19)
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#define OMAP5430_MASK_CLEAR_MPU_MASK BIT(18)
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#define OMAP5430_MASK_CLEAR_ACCUM_CORE_MASK BIT(17)
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#define OMAP5430_MASK_CLEAR_ACCUM_GPU_MASK BIT(16)
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#define OMAP5430_MASK_CLEAR_ACCUM_MPU_MASK BIT(15)
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#define OMAP5430_MASK_HOT_CORE_MASK BIT(5)
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#define OMAP5430_MASK_COLD_CORE_MASK BIT(4)
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#define OMAP5430_MASK_HOT_GPU_MASK BIT(3)
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#define OMAP5430_MASK_COLD_GPU_MASK BIT(2)
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#define OMAP5430_MASK_HOT_MPU_MASK BIT(1)
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#define OMAP5430_MASK_COLD_MPU_MASK BIT(0)
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/* OMAP5430.BANDGAP_COUNTER */
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#define OMAP5430_COUNTER_MASK (0xffffff << 0)
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/* OMAP5430.BANDGAP_THRESHOLD */
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#define OMAP5430_T_HOT_MASK (0x3ff << 16)
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#define OMAP5430_T_COLD_MASK (0x3ff << 0)
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/* OMAP5430.TSHUT_THRESHOLD */
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#define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16)
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#define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0)
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/* OMAP5430.BANDGAP_CUMUL_DTEMP_MPU */
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#define OMAP5430_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
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/* OMAP5430.BANDGAP_CUMUL_DTEMP_GPU */
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#define OMAP5430_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
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/* OMAP5430.BANDGAP_CUMUL_DTEMP_CORE */
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#define OMAP5430_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
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/* OMAP5430.BANDGAP_STATUS */
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#define OMAP5430_BGAP_ALERT_MASK BIT(31)
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#define OMAP5430_HOT_CORE_FLAG_MASK BIT(5)
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#define OMAP5430_COLD_CORE_FLAG_MASK BIT(4)
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#define OMAP5430_HOT_GPU_FLAG_MASK BIT(3)
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#define OMAP5430_COLD_GPU_FLAG_MASK BIT(2)
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#define OMAP5430_HOT_MPU_FLAG_MASK BIT(1)
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#define OMAP5430_COLD_MPU_FLAG_MASK BIT(0)
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/**
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* Temperature limits and thresholds for OMAP5430
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*
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* All the macros bellow are definitions for handling the
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* ADC conversions and representation of temperature limits
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* and thresholds for OMAP5430. Definitions are grouped
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* by temperature domain.
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*/
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/* OMAP5430.common temperature definitions */
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/* ADC conversion table limits */
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#define OMAP5430_ADC_START_VALUE 540
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#define OMAP5430_ADC_END_VALUE 945
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/* OMAP5430.GPU temperature definitions */
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/* bandgap clock limits */
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#define OMAP5430_GPU_MAX_FREQ 1500000
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#define OMAP5430_GPU_MIN_FREQ 1000000
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/* sensor limits */
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#define OMAP5430_GPU_MIN_TEMP -40000
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#define OMAP5430_GPU_MAX_TEMP 125000
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#define OMAP5430_GPU_HYST_VAL 5000
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/* interrupts thresholds */
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#define OMAP5430_GPU_TSHUT_HOT 915
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#define OMAP5430_GPU_TSHUT_COLD 900
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#define OMAP5430_GPU_T_HOT 800
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#define OMAP5430_GPU_T_COLD 795
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/* OMAP5430.MPU temperature definitions */
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/* bandgap clock limits */
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#define OMAP5430_MPU_MAX_FREQ 1500000
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#define OMAP5430_MPU_MIN_FREQ 1000000
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/* sensor limits */
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#define OMAP5430_MPU_MIN_TEMP -40000
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#define OMAP5430_MPU_MAX_TEMP 125000
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#define OMAP5430_MPU_HYST_VAL 5000
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/* interrupts thresholds */
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#define OMAP5430_MPU_TSHUT_HOT 915
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#define OMAP5430_MPU_TSHUT_COLD 900
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#define OMAP5430_MPU_T_HOT 800
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#define OMAP5430_MPU_T_COLD 795
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/* OMAP5430.CORE temperature definitions */
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/* bandgap clock limits */
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#define OMAP5430_CORE_MAX_FREQ 1500000
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#define OMAP5430_CORE_MIN_FREQ 1000000
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/* sensor limits */
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#define OMAP5430_CORE_MIN_TEMP -40000
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#define OMAP5430_CORE_MAX_TEMP 125000
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#define OMAP5430_CORE_HYST_VAL 5000
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/* interrupts thresholds */
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#define OMAP5430_CORE_TSHUT_HOT 915
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#define OMAP5430_CORE_TSHUT_COLD 900
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#define OMAP5430_CORE_T_HOT 800
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#define OMAP5430_CORE_T_COLD 795
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#endif /* __OMAP5XXX_BANDGAP_H */
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