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![Alan Cox](/assets/img/avatar_default.png)
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
373 lines
12 KiB
C
373 lines
12 KiB
C
/*
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* Agere Systems Inc.
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* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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* http://www.agere.com
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*
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*------------------------------------------------------------------------------
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*
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* et1310_rx.h - Defines, structs, enums, prototypes, etc. pertaining to data
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* reception.
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*
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*------------------------------------------------------------------------------
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*
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* SOFTWARE LICENSE
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*
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* This software is provided subject to the following terms and conditions,
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* which you should read carefully before using the software. Using this
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* software indicates your acceptance of these terms and conditions. If you do
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* not agree with these terms and conditions, do not use the software.
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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*
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* Redistribution and use in source or binary forms, with or without
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* modifications, are permitted provided that the following conditions are met:
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*
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* . Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following Disclaimer as comments in the code as
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* well as in the documentation and/or other materials provided with the
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* distribution.
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*
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* . Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following Disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* . Neither the name of Agere Systems Inc. nor the names of the contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* Disclaimer
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
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* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#ifndef __ET1310_RX_H__
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#define __ET1310_RX_H__
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#include "et1310_address_map.h"
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#define USE_FBR0 true
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#ifdef USE_FBR0
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/* #define FBR0_BUFFER_SIZE 256 */
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#endif
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/* #define FBR1_BUFFER_SIZE 2048 */
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#define FBR_CHUNKS 32
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#define MAX_DESC_PER_RING_RX 1024
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/* number of RFDs - default and min */
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#ifdef USE_FBR0
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#define RFD_LOW_WATER_MARK 40
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#define NIC_MIN_NUM_RFD 64
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#define NIC_DEFAULT_NUM_RFD 1024
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#else
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#define RFD_LOW_WATER_MARK 20
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#define NIC_MIN_NUM_RFD 64
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#define NIC_DEFAULT_NUM_RFD 256
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#endif
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#define NUM_PACKETS_HANDLED 256
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#define ALCATEL_BAD_STATUS 0xe47f0000
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#define ALCATEL_MULTICAST_PKT 0x01000000
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#define ALCATEL_BROADCAST_PKT 0x02000000
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/* typedefs for Free Buffer Descriptors */
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typedef union _FBR_WORD2_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 reserved:22; /* bits 10-31 */
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u32 bi:10; /* bits 0-9(Buffer Index) */
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#else
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u32 bi:10; /* bits 0-9(Buffer Index) */
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u32 reserved:22; /* bit 10-31 */
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#endif
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} bits;
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} FBR_WORD2_t, *PFBR_WORD2_t;
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typedef struct _FBR_DESC_t {
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u32 addr_lo;
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u32 addr_hi;
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FBR_WORD2_t word2;
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} FBR_DESC_t, *PFBR_DESC_t;
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/* Typedefs for Packet Status Ring Descriptors */
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typedef union _PKT_STAT_DESC_WORD0_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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/* top 16 bits are from the Alcatel Status Word as enumerated in */
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/* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) */
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#if 0
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u32 asw_trunc:1; /* bit 31(Rx frame truncated) */
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#endif
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u32 asw_long_evt:1; /* bit 31(Rx long event) */
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u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */
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u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */
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u32 asw_pause_frame:1; /* bit 28(is a pause frame) */
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u32 asw_control_frame:1; /* bit 27(is a control frame) */
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u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */
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u32 asw_broadcast:1; /* bit 25(has a broadcast address) */
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u32 asw_multicast:1; /* bit 24(has a multicast address) */
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u32 asw_OK:1; /* bit 23(valid CRC + no code error) */
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u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */
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u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */
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u32 asw_CRC_err:1; /* bit 20(CRC error) */
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u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */
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u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */
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u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */
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u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */
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u32 unused:5; /* bits 11-15 */
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u32 vp:1; /* bit 10(VLAN Packet) */
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u32 jp:1; /* bit 9(Jumbo Packet) */
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u32 ft:1; /* bit 8(Frame Truncated) */
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u32 drop:1; /* bit 7(Drop packet) */
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u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */
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u32 wol:1; /* bit 5(WOL Event) */
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u32 tcpp:1; /* bit 4(TCP checksum pass) */
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u32 tcpa:1; /* bit 3(TCP checksum assist) */
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u32 ipp:1; /* bit 2(IP checksum pass) */
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u32 ipa:1; /* bit 1(IP checksum assist) */
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u32 hp:1; /* bit 0(hash pass) */
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#else
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u32 hp:1; /* bit 0(hash pass) */
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u32 ipa:1; /* bit 1(IP checksum assist) */
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u32 ipp:1; /* bit 2(IP checksum pass) */
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u32 tcpa:1; /* bit 3(TCP checksum assist) */
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u32 tcpp:1; /* bit 4(TCP checksum pass) */
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u32 wol:1; /* bit 5(WOL Event) */
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u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */
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u32 drop:1; /* bit 7(Drop packet) */
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u32 ft:1; /* bit 8(Frame Truncated) */
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u32 jp:1; /* bit 9(Jumbo Packet) */
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u32 vp:1; /* bit 10(VLAN Packet) */
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u32 unused:5; /* bits 11-15 */
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u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */
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u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */
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u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */
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u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */
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u32 asw_CRC_err:1; /* bit 20(CRC error) */
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u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */
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u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */
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u32 asw_OK:1; /* bit 23(valid CRC + no code error) */
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u32 asw_multicast:1; /* bit 24(has a multicast address) */
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u32 asw_broadcast:1; /* bit 25(has a broadcast address) */
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u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */
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u32 asw_control_frame:1; /* bit 27(is a control frame) */
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u32 asw_pause_frame:1; /* bit 28(is a pause frame) */
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u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */
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u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */
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u32 asw_long_evt:1; /* bit 31(Rx long event) */
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#if 0
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u32 asw_trunc:1; /* bit 31(Rx frame truncated) */
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#endif
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#endif
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} bits;
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} PKT_STAT_DESC_WORD0_t, *PPKT_STAT_WORD0_t;
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typedef union _PKT_STAT_DESC_WORD1_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 unused:4; /* bits 28-31 */
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u32 ri:2; /* bits 26-27(Ring Index) */
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u32 bi:10; /* bits 16-25(Buffer Index) */
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u32 length:16; /* bit 0-15(length in bytes) */
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#else
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u32 length:16; /* bit 0-15(length in bytes) */
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u32 bi:10; /* bits 16-25(Buffer Index) */
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u32 ri:2; /* bits 26-27(Ring Index) */
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u32 unused:4; /* bits 28-31 */
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#endif
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} bits;
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} PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t;
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typedef struct _PKT_STAT_DESC_t {
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PKT_STAT_DESC_WORD0_t word0;
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PKT_STAT_DESC_WORD1_t word1;
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} PKT_STAT_DESC_t, *PPKT_STAT_DESC_t;
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/* Typedefs for the RX DMA status word */
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/*
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* RXSTAT_WORD0_t structure holds part of the status bits of the Rx DMA engine
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* that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
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* whichcontains Free Buffer ring 0 and 1 available offset.
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*/
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typedef union _rxstat_word0_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 FBR1unused:5; /* bits 27-31 */
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u32 FBR1wrap:1; /* bit 26 */
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u32 FBR1offset:10; /* bits 16-25 */
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u32 FBR0unused:5; /* bits 11-15 */
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u32 FBR0wrap:1; /* bit 10 */
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u32 FBR0offset:10; /* bits 0-9 */
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#else
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u32 FBR0offset:10; /* bits 0-9 */
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u32 FBR0wrap:1; /* bit 10 */
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u32 FBR0unused:5; /* bits 11-15 */
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u32 FBR1offset:10; /* bits 16-25 */
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u32 FBR1wrap:1; /* bit 26 */
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u32 FBR1unused:5; /* bits 27-31 */
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#endif
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} bits;
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} RXSTAT_WORD0_t, *PRXSTAT_WORD0_t;
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/*
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* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
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* that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
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* which contains the Packet Status Ring available offset.
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*/
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typedef union _rxstat_word1_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 PSRunused:3; /* bits 29-31 */
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u32 PSRwrap:1; /* bit 28 */
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u32 PSRoffset:12; /* bits 16-27 */
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u32 reserved:16; /* bits 0-15 */
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#else
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u32 reserved:16; /* bits 0-15 */
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u32 PSRoffset:12; /* bits 16-27 */
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u32 PSRwrap:1; /* bit 28 */
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u32 PSRunused:3; /* bits 29-31 */
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#endif
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} bits;
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} RXSTAT_WORD1_t, *PRXSTAT_WORD1_t;
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/*
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* RX_STATUS_BLOCK_t is sructure representing the status of the Rx DMA engine
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* it sits in free memory, and is pointed to by 0x101c / 0x1020
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*/
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typedef struct _rx_status_block_t {
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RXSTAT_WORD0_t Word0;
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RXSTAT_WORD1_t Word1;
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} RX_STATUS_BLOCK_t, *PRX_STATUS_BLOCK_t;
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/*
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* Structure for look-up table holding free buffer ring pointers
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*/
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typedef struct _FbrLookupTable {
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void *Va[MAX_DESC_PER_RING_RX];
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void *Buffer1[MAX_DESC_PER_RING_RX];
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void *Buffer2[MAX_DESC_PER_RING_RX];
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u32 PAHigh[MAX_DESC_PER_RING_RX];
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u32 PALow[MAX_DESC_PER_RING_RX];
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} FBRLOOKUPTABLE, *PFBRLOOKUPTABLE;
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typedef enum {
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ONE_PACKET_INTERRUPT,
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FOUR_PACKET_INTERRUPT
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} eRX_INTERRUPT_STATE_t, *PeRX_INTERRUPT_STATE_t;
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/*
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* Structure to hold the skb's in a list
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*/
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typedef struct rx_skb_list_elem {
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struct list_head skb_list_elem;
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dma_addr_t dma_addr;
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struct sk_buff *skb;
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} RX_SKB_LIST_ELEM, *PRX_SKB_LIST_ELEM;
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/*
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* RX_RING_t is sructure representing the adaptor's local reference(s) to the
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* rings
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*/
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typedef struct _rx_ring_t {
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#ifdef USE_FBR0
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void *pFbr0RingVa;
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dma_addr_t pFbr0RingPa;
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void *Fbr0MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
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dma_addr_t Fbr0MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
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uint64_t Fbr0Realpa;
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uint64_t Fbr0offset;
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u32 local_Fbr0_full;
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u32 Fbr0NumEntries;
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u32 Fbr0BufferSize;
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#endif
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void *pFbr1RingVa;
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dma_addr_t pFbr1RingPa;
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void *Fbr1MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
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dma_addr_t Fbr1MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
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uint64_t Fbr1Realpa;
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uint64_t Fbr1offset;
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FBRLOOKUPTABLE *Fbr[2];
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u32 local_Fbr1_full;
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u32 Fbr1NumEntries;
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u32 Fbr1BufferSize;
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void *pPSRingVa;
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dma_addr_t pPSRingPa;
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uint64_t pPSRingRealPa;
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uint64_t pPSRingOffset;
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RXDMA_PSR_FULL_OFFSET_t local_psr_full;
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u32 PsrNumEntries;
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void *pRxStatusVa;
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dma_addr_t pRxStatusPa;
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uint64_t RxStatusRealPA;
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uint64_t RxStatusOffset;
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struct list_head RecvBufferPool;
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/* RECV */
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struct list_head RecvList;
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struct list_head RecvPendingList;
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u32 nReadyRecv;
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u32 NumRfd;
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bool UnfinishedReceives;
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struct list_head RecvPacketPool;
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/* lookaside lists */
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struct kmem_cache *RecvLookaside;
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} RX_RING_t, *PRX_RING_t;
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/* Forward reference of RFD */
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struct _MP_RFD;
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/* Forward declaration of the private adapter structure */
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struct et131x_adapter;
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/* PROTOTYPES for Initialization */
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int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter);
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void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
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int et131x_rfd_resources_alloc(struct et131x_adapter *adapter,
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struct _MP_RFD *pMpRfd);
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void et131x_rfd_resources_free(struct et131x_adapter *adapter,
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struct _MP_RFD *pMpRfd);
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int et131x_init_recv(struct et131x_adapter *adapter);
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void ConfigRxDmaRegs(struct et131x_adapter *adapter);
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void SetRxDmaTimer(struct et131x_adapter *adapter);
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void et131x_rx_dma_disable(struct et131x_adapter *adapter);
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void et131x_rx_dma_enable(struct et131x_adapter *adapter);
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void et131x_reset_recv(struct et131x_adapter *adapter);
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void et131x_handle_recv_interrupt(struct et131x_adapter *adapter);
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#endif /* __ET1310_RX_H__ */
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