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![Chaithrika U S](/assets/img/avatar_default.png)
McASP write FIFO registers should be modified for playback and read FIFO registers for capture. Check the PCM mode before manipulating the FIFO registers. Currently, irrespective of playback/capture both the FIFOs are enabled or disbaled. This resulted in errors in audio loopback mode. Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
969 lines
25 KiB
C
969 lines
25 KiB
C
/*
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* ALSA SoC McASP Audio Layer for TI DAVINCI processor
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*
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* Multi-channel Audio Serial Port Driver
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*
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* Author: Nirmal Pandey <n-pandey@ti.com>,
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* Suresh Rajashekara <suresh.r@ti.com>
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* Steve Chen <schen@.mvista.com>
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*
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* Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
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* Copyright: (C) 2009 Texas Instruments, India
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include "davinci-pcm.h"
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#include "davinci-mcasp.h"
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/*
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* McASP register definitions
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*/
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#define DAVINCI_MCASP_PID_REG 0x00
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#define DAVINCI_MCASP_PWREMUMGT_REG 0x04
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#define DAVINCI_MCASP_PFUNC_REG 0x10
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#define DAVINCI_MCASP_PDIR_REG 0x14
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#define DAVINCI_MCASP_PDOUT_REG 0x18
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#define DAVINCI_MCASP_PDSET_REG 0x1c
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#define DAVINCI_MCASP_PDCLR_REG 0x20
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#define DAVINCI_MCASP_TLGC_REG 0x30
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#define DAVINCI_MCASP_TLMR_REG 0x34
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#define DAVINCI_MCASP_GBLCTL_REG 0x44
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#define DAVINCI_MCASP_AMUTE_REG 0x48
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#define DAVINCI_MCASP_LBCTL_REG 0x4c
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#define DAVINCI_MCASP_TXDITCTL_REG 0x50
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#define DAVINCI_MCASP_GBLCTLR_REG 0x60
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#define DAVINCI_MCASP_RXMASK_REG 0x64
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#define DAVINCI_MCASP_RXFMT_REG 0x68
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#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
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#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
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#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
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#define DAVINCI_MCASP_RXTDM_REG 0x78
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#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
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#define DAVINCI_MCASP_RXSTAT_REG 0x80
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#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
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#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
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#define DAVINCI_MCASP_REVTCTL_REG 0x8c
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#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
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#define DAVINCI_MCASP_TXMASK_REG 0xa4
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#define DAVINCI_MCASP_TXFMT_REG 0xa8
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#define DAVINCI_MCASP_TXFMCTL_REG 0xac
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#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
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#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
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#define DAVINCI_MCASP_TXTDM_REG 0xb8
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#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
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#define DAVINCI_MCASP_TXSTAT_REG 0xc0
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#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
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#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
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#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
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/* Left(even TDM Slot) Channel Status Register File */
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#define DAVINCI_MCASP_DITCSRA_REG 0x100
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/* Right(odd TDM slot) Channel Status Register File */
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#define DAVINCI_MCASP_DITCSRB_REG 0x118
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/* Left(even TDM slot) User Data Register File */
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#define DAVINCI_MCASP_DITUDRA_REG 0x130
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/* Right(odd TDM Slot) User Data Register File */
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#define DAVINCI_MCASP_DITUDRB_REG 0x148
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/* Serializer n Control Register */
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#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
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#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
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(n << 2))
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/* Transmit Buffer for Serializer n */
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#define DAVINCI_MCASP_TXBUF_REG 0x200
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/* Receive Buffer for Serializer n */
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#define DAVINCI_MCASP_RXBUF_REG 0x280
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/* McASP FIFO Registers */
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#define DAVINCI_MCASP_WFIFOCTL (0x1010)
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#define DAVINCI_MCASP_WFIFOSTS (0x1014)
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#define DAVINCI_MCASP_RFIFOCTL (0x1018)
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#define DAVINCI_MCASP_RFIFOSTS (0x101C)
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/*
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* DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
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* Register Bits
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*/
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#define MCASP_FREE BIT(0)
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#define MCASP_SOFT BIT(1)
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/*
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* DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
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*/
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#define AXR(n) (1<<n)
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#define PFUNC_AMUTE BIT(25)
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#define ACLKX BIT(26)
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#define AHCLKX BIT(27)
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#define AFSX BIT(28)
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#define ACLKR BIT(29)
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#define AHCLKR BIT(30)
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#define AFSR BIT(31)
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/*
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* DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
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*/
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#define AXR(n) (1<<n)
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#define PDIR_AMUTE BIT(25)
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#define ACLKX BIT(26)
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#define AHCLKX BIT(27)
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#define AFSX BIT(28)
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#define ACLKR BIT(29)
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#define AHCLKR BIT(30)
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#define AFSR BIT(31)
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/*
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* DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
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*/
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#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
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#define VA BIT(2)
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#define VB BIT(3)
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/*
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* DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
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*/
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#define TXROT(val) (val)
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#define TXSEL BIT(3)
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#define TXSSZ(val) (val<<4)
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#define TXPBIT(val) (val<<8)
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#define TXPAD(val) (val<<13)
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#define TXORD BIT(15)
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#define FSXDLY(val) (val<<16)
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/*
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* DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
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*/
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#define RXROT(val) (val)
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#define RXSEL BIT(3)
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#define RXSSZ(val) (val<<4)
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#define RXPBIT(val) (val<<8)
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#define RXPAD(val) (val<<13)
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#define RXORD BIT(15)
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#define FSRDLY(val) (val<<16)
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/*
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* DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
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*/
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#define FSXPOL BIT(0)
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#define AFSXE BIT(1)
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#define FSXDUR BIT(4)
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#define FSXMOD(val) (val<<7)
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/*
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* DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
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*/
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#define FSRPOL BIT(0)
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#define AFSRE BIT(1)
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#define FSRDUR BIT(4)
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#define FSRMOD(val) (val<<7)
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/*
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* DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
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*/
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#define ACLKXDIV(val) (val)
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#define ACLKXE BIT(5)
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#define TX_ASYNC BIT(6)
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#define ACLKXPOL BIT(7)
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/*
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* DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
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*/
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#define ACLKRDIV(val) (val)
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#define ACLKRE BIT(5)
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#define RX_ASYNC BIT(6)
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#define ACLKRPOL BIT(7)
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/*
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* DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
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* Register Bits
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*/
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#define AHCLKXDIV(val) (val)
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#define AHCLKXPOL BIT(14)
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#define AHCLKXE BIT(15)
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/*
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* DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
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* Register Bits
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*/
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#define AHCLKRDIV(val) (val)
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#define AHCLKRPOL BIT(14)
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#define AHCLKRE BIT(15)
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/*
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* DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
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*/
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#define MODE(val) (val)
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#define DISMOD (val)(val<<2)
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#define TXSTATE BIT(4)
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#define RXSTATE BIT(5)
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/*
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* DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
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*/
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#define LBEN BIT(0)
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#define LBORD BIT(1)
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#define LBGENMODE(val) (val<<2)
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/*
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* DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
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*/
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#define TXTDMS(n) (1<<n)
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/*
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* DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
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*/
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#define RXTDMS(n) (1<<n)
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/*
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* DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
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*/
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#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
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#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
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#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
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#define RXSMRST BIT(3) /* Receiver State Machine Reset */
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#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
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#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
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#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
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#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
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#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
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#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
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/*
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* DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
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*/
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#define MUTENA(val) (val)
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#define MUTEINPOL BIT(2)
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#define MUTEINENA BIT(3)
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#define MUTEIN BIT(4)
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#define MUTER BIT(5)
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#define MUTEX BIT(6)
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#define MUTEFSR BIT(7)
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#define MUTEFSX BIT(8)
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#define MUTEBADCLKR BIT(9)
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#define MUTEBADCLKX BIT(10)
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#define MUTERXDMAERR BIT(11)
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#define MUTETXDMAERR BIT(12)
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/*
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* DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
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*/
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#define RXDATADMADIS BIT(0)
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/*
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* DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
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*/
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#define TXDATADMADIS BIT(0)
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/*
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* DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
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*/
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#define FIFO_ENABLE BIT(16)
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#define NUMEVT_MASK (0xFF << 8)
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#define NUMDMA_MASK (0xFF)
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#define DAVINCI_MCASP_NUM_SERIALIZER 16
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static inline void mcasp_set_bits(void __iomem *reg, u32 val)
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{
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__raw_writel(__raw_readl(reg) | val, reg);
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}
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static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
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{
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__raw_writel((__raw_readl(reg) & ~(val)), reg);
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}
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static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
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{
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__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
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}
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static inline void mcasp_set_reg(void __iomem *reg, u32 val)
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{
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__raw_writel(val, reg);
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}
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static inline u32 mcasp_get_reg(void __iomem *reg)
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{
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return (unsigned int)__raw_readl(reg);
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}
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static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
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{
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int i = 0;
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mcasp_set_bits(regs, val);
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/* programming GBLCTL needs to read back from GBLCTL and verfiy */
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/* loop count is to avoid the lock-up */
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for (i = 0; i < 1000; i++) {
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if ((mcasp_get_reg(regs) & val) == val)
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break;
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}
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if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
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printk(KERN_ERR "GBLCTL write error\n");
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}
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static void mcasp_start_rx(struct davinci_audio_dev *dev)
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{
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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}
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static void mcasp_start_tx(struct davinci_audio_dev *dev)
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{
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u8 offset = 0, i;
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u32 cnt;
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
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mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
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for (i = 0; i < dev->num_serializer; i++) {
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if (dev->serial_dir[i] == TX_MODE) {
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offset = i;
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break;
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}
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}
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/* wait for TX ready */
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cnt = 0;
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while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
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TXSTATE) && (cnt < 100000))
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cnt++;
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mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
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}
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static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
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{
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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if (dev->txnumevt) /* enable FIFO */
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mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
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FIFO_ENABLE);
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mcasp_start_tx(dev);
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} else {
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if (dev->rxnumevt) /* enable FIFO */
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mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
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FIFO_ENABLE);
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mcasp_start_rx(dev);
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}
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}
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static void mcasp_stop_rx(struct davinci_audio_dev *dev)
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{
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mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
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}
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static void mcasp_stop_tx(struct davinci_audio_dev *dev)
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{
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mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
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}
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static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
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{
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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if (dev->txnumevt) /* disable FIFO */
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mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
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FIFO_ENABLE);
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mcasp_stop_tx(dev);
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} else {
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if (dev->rxnumevt) /* disable FIFO */
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mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
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FIFO_ENABLE);
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mcasp_stop_rx(dev);
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}
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}
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static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct davinci_audio_dev *dev = cpu_dai->private_data;
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void __iomem *base = dev->base;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* codec is clock and frame slave */
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mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
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mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));
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break;
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case SND_SOC_DAIFMT_CBM_CFS:
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/* codec is clock master and frame slave */
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mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
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mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
|
|
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x2d << 26));
|
|
break;
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
/* codec is clock and frame master */
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26));
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_NB_IF:
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
|
mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
|
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
|
mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
|
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int davinci_config_channel_size(struct davinci_audio_dev *dev,
|
|
int channel_size)
|
|
{
|
|
u32 fmt = 0;
|
|
u32 mask, rotate;
|
|
|
|
switch (channel_size) {
|
|
case DAVINCI_AUDIO_WORD_8:
|
|
fmt = 0x03;
|
|
rotate = 6;
|
|
mask = 0x000000ff;
|
|
break;
|
|
|
|
case DAVINCI_AUDIO_WORD_12:
|
|
fmt = 0x05;
|
|
rotate = 5;
|
|
mask = 0x00000fff;
|
|
break;
|
|
|
|
case DAVINCI_AUDIO_WORD_16:
|
|
fmt = 0x07;
|
|
rotate = 4;
|
|
mask = 0x0000ffff;
|
|
break;
|
|
|
|
case DAVINCI_AUDIO_WORD_20:
|
|
fmt = 0x09;
|
|
rotate = 3;
|
|
mask = 0x000fffff;
|
|
break;
|
|
|
|
case DAVINCI_AUDIO_WORD_24:
|
|
fmt = 0x0B;
|
|
rotate = 2;
|
|
mask = 0x00ffffff;
|
|
break;
|
|
|
|
case DAVINCI_AUDIO_WORD_28:
|
|
fmt = 0x0D;
|
|
rotate = 1;
|
|
mask = 0x0fffffff;
|
|
break;
|
|
|
|
case DAVINCI_AUDIO_WORD_32:
|
|
fmt = 0x0F;
|
|
rotate = 0;
|
|
mask = 0xffffffff;
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
|
|
RXSSZ(fmt), RXSSZ(0x0F));
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
|
|
TXSSZ(fmt), TXSSZ(0x0F));
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
|
|
TXROT(7));
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
|
|
RXROT(7));
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
|
|
{
|
|
int i;
|
|
u8 tx_ser = 0;
|
|
u8 rx_ser = 0;
|
|
|
|
/* Default configuration */
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
|
|
|
|
/* All PINS as McASP */
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
|
|
|
|
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
|
|
TXDATADMADIS);
|
|
} else {
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
|
|
RXDATADMADIS);
|
|
}
|
|
|
|
for (i = 0; i < dev->num_serializer; i++) {
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
|
|
dev->serial_dir[i]);
|
|
if (dev->serial_dir[i] == TX_MODE) {
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
|
|
AXR(i));
|
|
tx_ser++;
|
|
} else if (dev->serial_dir[i] == RX_MODE) {
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
|
|
AXR(i));
|
|
rx_ser++;
|
|
}
|
|
}
|
|
|
|
if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
if (dev->txnumevt * tx_ser > 64)
|
|
dev->txnumevt = 1;
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
|
|
NUMDMA_MASK);
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
|
|
((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
|
|
}
|
|
|
|
if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
|
|
if (dev->rxnumevt * rx_ser > 64)
|
|
dev->rxnumevt = 1;
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
|
|
NUMDMA_MASK);
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
|
|
((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
|
|
}
|
|
}
|
|
|
|
static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
|
|
{
|
|
int i, active_slots;
|
|
u32 mask = 0;
|
|
|
|
active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
|
|
for (i = 0; i < active_slots; i++)
|
|
mask |= (1 << i);
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
|
|
|
|
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
/* bit stream is MSB first with no delay */
|
|
/* DSP_B mode */
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
|
|
AHCLKXE);
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
|
|
|
|
if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
|
|
FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
|
|
else
|
|
printk(KERN_ERR "playback tdm slot %d not supported\n",
|
|
dev->tdm_slots);
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
|
|
} else {
|
|
/* bit stream is MSB first with no delay */
|
|
/* DSP_B mode */
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
|
|
AHCLKRE);
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
|
|
|
|
if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
|
|
FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
|
|
else
|
|
printk(KERN_ERR "capture tdm slot %d not supported\n",
|
|
dev->tdm_slots);
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
|
|
}
|
|
}
|
|
|
|
/* S/PDIF */
|
|
static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
|
|
{
|
|
/* Set the PDIR for Serialiser as output */
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
|
|
|
|
/* TXMASK for 24 bits */
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
|
|
|
|
/* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
|
|
and LSB first */
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
|
|
TXROT(6) | TXSSZ(15));
|
|
|
|
/* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
|
|
AFSXE | FSXMOD(0x180));
|
|
|
|
/* Set the TX tdm : for all the slots */
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
|
|
|
|
/* Set the TX clock controls : div = 1 and internal */
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
|
|
ACLKXE | TX_ASYNC);
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
|
|
|
|
/* Only 44100 and 48000 are valid, both have the same setting */
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
|
|
|
|
/* Enable the DIT */
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
|
|
}
|
|
|
|
static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct davinci_audio_dev *dev = cpu_dai->private_data;
|
|
struct davinci_pcm_dma_params *dma_params =
|
|
&dev->dma_params[substream->stream];
|
|
int word_length;
|
|
u8 numevt;
|
|
|
|
davinci_hw_common_param(dev, substream->stream);
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
numevt = dev->txnumevt;
|
|
else
|
|
numevt = dev->rxnumevt;
|
|
|
|
if (!numevt)
|
|
numevt = 1;
|
|
|
|
if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
|
|
davinci_hw_dit_param(dev);
|
|
else
|
|
davinci_hw_param(dev, substream->stream);
|
|
|
|
switch (params_format(params)) {
|
|
case SNDRV_PCM_FORMAT_S8:
|
|
dma_params->data_type = 1;
|
|
word_length = DAVINCI_AUDIO_WORD_8;
|
|
break;
|
|
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
|
dma_params->data_type = 2;
|
|
word_length = DAVINCI_AUDIO_WORD_16;
|
|
break;
|
|
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
|
dma_params->data_type = 4;
|
|
word_length = DAVINCI_AUDIO_WORD_32;
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (dev->version == MCASP_VERSION_2) {
|
|
dma_params->data_type *= numevt;
|
|
dma_params->acnt = 4 * numevt;
|
|
} else
|
|
dma_params->acnt = dma_params->data_type;
|
|
|
|
davinci_config_channel_size(dev, word_length);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
|
|
int cmd, struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
|
struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data;
|
|
int ret = 0;
|
|
|
|
switch (cmd) {
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
davinci_mcasp_start(dev, substream->stream);
|
|
break;
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
davinci_mcasp_stop(dev, substream->stream);
|
|
break;
|
|
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
|
|
.trigger = davinci_mcasp_trigger,
|
|
.hw_params = davinci_mcasp_hw_params,
|
|
.set_fmt = davinci_mcasp_set_dai_fmt,
|
|
|
|
};
|
|
|
|
struct snd_soc_dai davinci_mcasp_dai[] = {
|
|
{
|
|
.name = "davinci-i2s",
|
|
.id = 0,
|
|
.playback = {
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.rates = DAVINCI_MCASP_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S8 |
|
|
SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
.capture = {
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.rates = DAVINCI_MCASP_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S8 |
|
|
SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
.ops = &davinci_mcasp_dai_ops,
|
|
|
|
},
|
|
{
|
|
.name = "davinci-dit",
|
|
.id = 1,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 384,
|
|
.rates = DAVINCI_MCASP_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
},
|
|
.ops = &davinci_mcasp_dai_ops,
|
|
},
|
|
|
|
};
|
|
EXPORT_SYMBOL_GPL(davinci_mcasp_dai);
|
|
|
|
static int davinci_mcasp_probe(struct platform_device *pdev)
|
|
{
|
|
struct davinci_pcm_dma_params *dma_data;
|
|
struct resource *mem, *ioarea, *res;
|
|
struct snd_platform_data *pdata;
|
|
struct davinci_audio_dev *dev;
|
|
int ret = 0;
|
|
|
|
dev = kzalloc(sizeof(struct davinci_audio_dev), GFP_KERNEL);
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!mem) {
|
|
dev_err(&pdev->dev, "no mem resource?\n");
|
|
ret = -ENODEV;
|
|
goto err_release_data;
|
|
}
|
|
|
|
ioarea = request_mem_region(mem->start,
|
|
(mem->end - mem->start) + 1, pdev->name);
|
|
if (!ioarea) {
|
|
dev_err(&pdev->dev, "Audio region already claimed\n");
|
|
ret = -EBUSY;
|
|
goto err_release_data;
|
|
}
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
dev->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(dev->clk)) {
|
|
ret = -ENODEV;
|
|
goto err_release_region;
|
|
}
|
|
|
|
clk_enable(dev->clk);
|
|
|
|
dev->base = (void __iomem *)IO_ADDRESS(mem->start);
|
|
dev->op_mode = pdata->op_mode;
|
|
dev->tdm_slots = pdata->tdm_slots;
|
|
dev->num_serializer = pdata->num_serializer;
|
|
dev->serial_dir = pdata->serial_dir;
|
|
dev->codec_fmt = pdata->codec_fmt;
|
|
dev->version = pdata->version;
|
|
dev->txnumevt = pdata->txnumevt;
|
|
dev->rxnumevt = pdata->rxnumevt;
|
|
|
|
dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
|
|
dma_data->eventq_no = pdata->eventq_no;
|
|
dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
|
|
io_v2p(dev->base));
|
|
|
|
/* first TX, then RX */
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "no DMA resource\n");
|
|
goto err_release_region;
|
|
}
|
|
|
|
dma_data->channel = res->start;
|
|
|
|
dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
|
|
dma_data->eventq_no = pdata->eventq_no;
|
|
dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
|
|
io_v2p(dev->base));
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "no DMA resource\n");
|
|
goto err_release_region;
|
|
}
|
|
|
|
dma_data->channel = res->start;
|
|
davinci_mcasp_dai[pdata->op_mode].private_data = dev;
|
|
davinci_mcasp_dai[pdata->op_mode].dev = &pdev->dev;
|
|
ret = snd_soc_register_dai(&davinci_mcasp_dai[pdata->op_mode]);
|
|
|
|
if (ret != 0)
|
|
goto err_release_region;
|
|
return 0;
|
|
|
|
err_release_region:
|
|
release_mem_region(mem->start, (mem->end - mem->start) + 1);
|
|
err_release_data:
|
|
kfree(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int davinci_mcasp_remove(struct platform_device *pdev)
|
|
{
|
|
struct snd_platform_data *pdata = pdev->dev.platform_data;
|
|
struct davinci_audio_dev *dev;
|
|
struct resource *mem;
|
|
|
|
snd_soc_unregister_dai(&davinci_mcasp_dai[pdata->op_mode]);
|
|
dev = davinci_mcasp_dai[pdata->op_mode].private_data;
|
|
clk_disable(dev->clk);
|
|
clk_put(dev->clk);
|
|
dev->clk = NULL;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(mem->start, (mem->end - mem->start) + 1);
|
|
|
|
kfree(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver davinci_mcasp_driver = {
|
|
.probe = davinci_mcasp_probe,
|
|
.remove = davinci_mcasp_remove,
|
|
.driver = {
|
|
.name = "davinci-mcasp",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init davinci_mcasp_init(void)
|
|
{
|
|
return platform_driver_register(&davinci_mcasp_driver);
|
|
}
|
|
module_init(davinci_mcasp_init);
|
|
|
|
static void __exit davinci_mcasp_exit(void)
|
|
{
|
|
platform_driver_unregister(&davinci_mcasp_driver);
|
|
}
|
|
module_exit(davinci_mcasp_exit);
|
|
|
|
MODULE_AUTHOR("Steve Chen");
|
|
MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
|
|
MODULE_LICENSE("GPL");
|
|
|