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linux-stable/arch/riscv/boot
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Conor Dooley 38a71fc048 riscv: dts: microchip: add mpfs's CAN controllers 
PolarFire SoC has a pair of CAN controllers, but as they were
undocumented there were omitted from the device tree. Add them.

Link: https://lore.kernel.org/all/20220607065459.2035746-3-conor.dooley@microchip.com
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-06-13 15:54:10 +02:00
..
dts riscv: dts: microchip: add mpfs's CAN controllers 2022-06-13 15:54:10 +02:00
.gitignore RISC-V: ignore xipImage 2022-05-24 17:52:37 -07:00
install.sh kbuild: factor out the common installation code into scripts/install.sh 2022-05-11 21:45:53 +09:00
loader.lds.S riscv: Move kernel mapping outside of linear mapping 2021-04-26 08:25:04 -07:00
loader.S riscv: provide a flat image loader 2019-11-17 15:17:39 -08:00
Makefile riscv: move the (z)install rules to arch/riscv/Makefile 2021-09-10 23:08:26 -07:00