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f120cd6533
In order to remove the crude hack where we sneak the masked bit into the timer's control register, make use of the phys_irq_map API control the active state of the interrupt. This causes some limited changes to allow for potential error propagation. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
81 lines
2.3 KiB
C
81 lines
2.3 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/compiler.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kvm_host.h>
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#include <linux/kvm.h>
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#include <asm/unified.h>
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#include <asm/ptrace.h>
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#include <asm/cputype.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_coproc.h>
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#include <kvm/arm_arch_timer.h>
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/******************************************************************************
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* Cortex-A15 and Cortex-A7 Reset Values
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*/
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static struct kvm_regs cortexa_regs_reset = {
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.usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
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};
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static const struct kvm_irq_level cortexa_vtimer_irq = {
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{ .irq = 27 },
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.level = 1,
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};
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/*******************************************************************************
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* Exported reset function
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*/
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/**
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* kvm_reset_vcpu - sets core registers and cp15 registers to reset value
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* @vcpu: The VCPU pointer
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*
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* This function finds the right table above and sets the registers on the
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* virtual CPU struct to their architectually defined reset values.
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*/
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int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
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{
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struct kvm_regs *reset_regs;
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const struct kvm_irq_level *cpu_vtimer_irq;
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switch (vcpu->arch.target) {
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case KVM_ARM_TARGET_CORTEX_A7:
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case KVM_ARM_TARGET_CORTEX_A15:
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reset_regs = &cortexa_regs_reset;
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vcpu->arch.midr = read_cpuid_id();
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cpu_vtimer_irq = &cortexa_vtimer_irq;
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break;
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default:
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return -ENODEV;
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}
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/* Reset core registers */
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memcpy(&vcpu->arch.regs, reset_regs, sizeof(vcpu->arch.regs));
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/* Reset CP15 registers */
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kvm_reset_coprocs(vcpu);
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/* Reset arch_timer context */
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return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
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}
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