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79ffac8599
In the current scheme, on submitting a request we take a single global GEM wakeref, which trickles down to wake up all GT power domains. This is undesirable as we would like to be able to localise our power management to the available power domains and to remove the global GEM operations from the heart of the driver. (The intent there is to push global GEM decisions to the boundary as used by the GEM user interface.) Now during request construction, each request is responsible via its logical context to acquire a wakeref on each power domain it intends to utilize. Currently, each request takes a wakeref on the engine(s) and the engines themselves take a chipset wakeref. This gives us a transition on each engine which we can extend if we want to insert more powermangement control (such as soft rc6). The global GEM operations that currently require a struct_mutex are reduced to listening to pm events from the chipset GT wakeref. As we reduce the struct_mutex requirement, these listeners should evaporate. Perhaps the biggest immediate change is that this removes the struct_mutex requirement around GT power management, allowing us greater flexibility in request construction. Another important knock-on effect, is that by tracking engine usage, we can insert a switch back to the kernel context on that engine immediately, avoiding any extra delay or inserting global synchronisation barriers. This makes tracking when an engine and its associated contexts are idle much easier -- important for when we forgo our assumed execution ordering and need idle barriers to unpin used contexts. In the process, it means we remove a large chunk of code whose only purpose was to switch back to the kernel context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
143 lines
3.4 KiB
C
143 lines
3.4 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_gt_pm.h"
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#include "intel_pm.h"
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#include "intel_wakeref.h"
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static void pm_notify(struct drm_i915_private *i915, int state)
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{
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blocking_notifier_call_chain(&i915->gt.pm_notifications, state, i915);
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}
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static int intel_gt_unpark(struct intel_wakeref *wf)
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{
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struct drm_i915_private *i915 =
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container_of(wf, typeof(*i915), gt.wakeref);
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GEM_TRACE("\n");
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/*
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* It seems that the DMC likes to transition between the DC states a lot
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* when there are no connected displays (no active power domains) during
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* command submission.
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*
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* This activity has negative impact on the performance of the chip with
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* huge latencies observed in the interrupt handler and elsewhere.
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*
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* Work around it by grabbing a GT IRQ power domain whilst there is any
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* GT activity, preventing any DC state transitions.
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*/
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i915->gt.awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
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GEM_BUG_ON(!i915->gt.awake);
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intel_enable_gt_powersave(i915);
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i915_update_gfx_val(i915);
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if (INTEL_GEN(i915) >= 6)
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gen6_rps_busy(i915);
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i915_pmu_gt_unparked(i915);
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i915_queue_hangcheck(i915);
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pm_notify(i915, INTEL_GT_UNPARK);
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return 0;
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}
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void intel_gt_pm_get(struct drm_i915_private *i915)
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{
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intel_wakeref_get(i915, &i915->gt.wakeref, intel_gt_unpark);
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}
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static int intel_gt_park(struct intel_wakeref *wf)
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{
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struct drm_i915_private *i915 =
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container_of(wf, typeof(*i915), gt.wakeref);
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intel_wakeref_t wakeref = fetch_and_zero(&i915->gt.awake);
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GEM_TRACE("\n");
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pm_notify(i915, INTEL_GT_PARK);
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i915_pmu_gt_parked(i915);
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if (INTEL_GEN(i915) >= 6)
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gen6_rps_idle(i915);
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GEM_BUG_ON(!wakeref);
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intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ, wakeref);
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return 0;
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}
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void intel_gt_pm_put(struct drm_i915_private *i915)
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{
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intel_wakeref_put(i915, &i915->gt.wakeref, intel_gt_park);
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}
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void intel_gt_pm_init(struct drm_i915_private *i915)
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{
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intel_wakeref_init(&i915->gt.wakeref);
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BLOCKING_INIT_NOTIFIER_HEAD(&i915->gt.pm_notifications);
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}
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static bool reset_engines(struct drm_i915_private *i915)
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{
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if (INTEL_INFO(i915)->gpu_reset_clobbers_display)
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return false;
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return intel_gpu_reset(i915, ALL_ENGINES) == 0;
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}
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/**
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* intel_gt_sanitize: called after the GPU has lost power
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* @i915: the i915 device
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* @force: ignore a failed reset and sanitize engine state anyway
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*
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* Anytime we reset the GPU, either with an explicit GPU reset or through a
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* PCI power cycle, the GPU loses state and we must reset our state tracking
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* to match. Note that calling intel_gt_sanitize() if the GPU has not
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* been reset results in much confusion!
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*/
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void intel_gt_sanitize(struct drm_i915_private *i915, bool force)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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GEM_TRACE("\n");
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if (!reset_engines(i915) && !force)
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return;
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for_each_engine(engine, i915, id)
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intel_engine_reset(engine, false);
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}
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void intel_gt_resume(struct drm_i915_private *i915)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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/*
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* After resume, we may need to poke into the pinned kernel
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* contexts to paper over any damage caused by the sudden suspend.
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* Only the kernel contexts should remain pinned over suspend,
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* allowing us to fixup the user contexts on their first pin.
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*/
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for_each_engine(engine, i915, id) {
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struct intel_context *ce;
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ce = engine->kernel_context;
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if (ce)
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ce->ops->reset(ce);
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ce = engine->preempt_context;
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if (ce)
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ce->ops->reset(ce);
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}
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}
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