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ea593dbba4
Previously, our view has been always to run the engines independently within a context. (Multiple engines happened before we had contexts and timelines, so they always operated independently and that behaviour persisted into contexts.) However, at the user level the context often represents a single timeline (e.g. GL contexts) and userspace must ensure that the individual engines are serialised to present that ordering to the client (or forgot about this detail entirely and hope no one notices - a fair ploy if the client can only directly control one engine themselves ;) In the next patch, we will want to construct a set of engines that operate as one, that have a single timeline interwoven between them, to present a single virtual engine to the user. (They submit to the virtual engine, then we decide which engine to execute on based.) To that end, we want to be able to create contexts which have a single timeline (fence context) shared between all engines, rather than multiple timelines. v2: Move the specialised timeline ordering to its own function. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190322092325.5883-4-chris@chris-wilson.co.uk
109 lines
2.9 KiB
C
109 lines
2.9 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* i915_sw_fence.h - library routines for N:M synchronisation points
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*
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* Copyright (C) 2016 Intel Corporation
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*/
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#ifndef _I915_SW_FENCE_H_
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#define _I915_SW_FENCE_H_
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#include <linux/dma-fence.h>
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#include <linux/gfp.h>
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#include <linux/kref.h>
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#include <linux/notifier.h> /* for NOTIFY_DONE */
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#include <linux/wait.h>
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struct completion;
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struct reservation_object;
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struct i915_sw_fence {
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wait_queue_head_t wait;
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unsigned long flags;
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atomic_t pending;
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};
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#define I915_SW_FENCE_CHECKED_BIT 0 /* used internally for DAG checking */
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#define I915_SW_FENCE_PRIVATE_BIT 1 /* available for use by owner */
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#define I915_SW_FENCE_MASK (~3)
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enum i915_sw_fence_notify {
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FENCE_COMPLETE,
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FENCE_FREE
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};
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typedef int (*i915_sw_fence_notify_t)(struct i915_sw_fence *,
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enum i915_sw_fence_notify state);
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#define __i915_sw_fence_call __aligned(4)
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void __i915_sw_fence_init(struct i915_sw_fence *fence,
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i915_sw_fence_notify_t fn,
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const char *name,
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struct lock_class_key *key);
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#ifdef CONFIG_LOCKDEP
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#define i915_sw_fence_init(fence, fn) \
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do { \
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static struct lock_class_key __key; \
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\
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__i915_sw_fence_init((fence), (fn), #fence, &__key); \
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} while (0)
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#else
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#define i915_sw_fence_init(fence, fn) \
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__i915_sw_fence_init((fence), (fn), NULL, NULL)
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#endif
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#ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
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void i915_sw_fence_fini(struct i915_sw_fence *fence);
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#else
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static inline void i915_sw_fence_fini(struct i915_sw_fence *fence) {}
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#endif
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void i915_sw_fence_commit(struct i915_sw_fence *fence);
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int i915_sw_fence_await_sw_fence(struct i915_sw_fence *fence,
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struct i915_sw_fence *after,
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wait_queue_entry_t *wq);
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int i915_sw_fence_await_sw_fence_gfp(struct i915_sw_fence *fence,
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struct i915_sw_fence *after,
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gfp_t gfp);
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struct i915_sw_dma_fence_cb {
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struct dma_fence_cb base;
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struct i915_sw_fence *fence;
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};
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int __i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence,
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struct dma_fence *dma,
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struct i915_sw_dma_fence_cb *cb);
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int i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence,
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struct dma_fence *dma,
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unsigned long timeout,
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gfp_t gfp);
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int i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
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struct reservation_object *resv,
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const struct dma_fence_ops *exclude,
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bool write,
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unsigned long timeout,
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gfp_t gfp);
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void i915_sw_fence_await(struct i915_sw_fence *fence);
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void i915_sw_fence_complete(struct i915_sw_fence *fence);
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static inline bool i915_sw_fence_signaled(const struct i915_sw_fence *fence)
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{
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return atomic_read(&fence->pending) <= 0;
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}
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static inline bool i915_sw_fence_done(const struct i915_sw_fence *fence)
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{
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return atomic_read(&fence->pending) < 0;
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}
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static inline void i915_sw_fence_wait(struct i915_sw_fence *fence)
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{
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wait_event(fence->wait, i915_sw_fence_done(fence));
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}
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#endif /* _I915_SW_FENCE_H_ */
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