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Add all clock outputs for the StarFive JH7100 audio clock generator. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20220126173953.1016706-4-kernel@esmil.dk Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
41 lines
1.3 KiB
C
41 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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*/
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#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
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#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
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#define JH7100_AUDCLK_ADC_MCLK 0
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#define JH7100_AUDCLK_I2S1_MCLK 1
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#define JH7100_AUDCLK_I2SADC_APB 2
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#define JH7100_AUDCLK_I2SADC_BCLK 3
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#define JH7100_AUDCLK_I2SADC_BCLK_N 4
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#define JH7100_AUDCLK_I2SADC_LRCLK 5
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#define JH7100_AUDCLK_PDM_APB 6
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#define JH7100_AUDCLK_PDM_MCLK 7
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#define JH7100_AUDCLK_I2SVAD_APB 8
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#define JH7100_AUDCLK_SPDIF 9
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#define JH7100_AUDCLK_SPDIF_APB 10
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#define JH7100_AUDCLK_PWMDAC_APB 11
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#define JH7100_AUDCLK_DAC_MCLK 12
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#define JH7100_AUDCLK_I2SDAC_APB 13
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#define JH7100_AUDCLK_I2SDAC_BCLK 14
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#define JH7100_AUDCLK_I2SDAC_BCLK_N 15
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#define JH7100_AUDCLK_I2SDAC_LRCLK 16
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#define JH7100_AUDCLK_I2S1_APB 17
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#define JH7100_AUDCLK_I2S1_BCLK 18
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#define JH7100_AUDCLK_I2S1_BCLK_N 19
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#define JH7100_AUDCLK_I2S1_LRCLK 20
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#define JH7100_AUDCLK_I2SDAC16K_APB 21
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#define JH7100_AUDCLK_APB0_BUS 22
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#define JH7100_AUDCLK_DMA1P_AHB 23
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#define JH7100_AUDCLK_USB_APB 24
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#define JH7100_AUDCLK_USB_LPM 25
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#define JH7100_AUDCLK_USB_STB 26
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#define JH7100_AUDCLK_APB_EN 27
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#define JH7100_AUDCLK_VAD_MEM 28
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#define JH7100_AUDCLK_END 29
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ */
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