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13ff3bdafd
These plls are found in the Tensor gs101 SoC found in the Pixel 6.
pll0516x: Integer PLL with high frequency
pll0517x: Integer PLL with middle frequency
pll0518x: Integer PLL with low frequency
PLL0516x
FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
PLL0517x and PLL0518x
FOUT = (MDIV * FIN)/PDIV*2^SDIV)
The PLLs are similar enough to pll_0822x that the same code can handle
both. The main difference is the change in the fout formula for the
high frequency 0516 pll.
Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
When defining the PLL the "con" parameter should be set to CON3
register, like this
PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
NULL),
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-8-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
118 lines
2.4 KiB
C
118 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Copyright (c) 2013 Linaro Ltd.
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*
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* Common Clock Framework support for all PLL's in Samsung platforms
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*/
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#ifndef __SAMSUNG_CLK_PLL_H
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#define __SAMSUNG_CLK_PLL_H
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enum samsung_pll_type {
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pll_2126,
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pll_3000,
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pll_35xx,
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pll_36xx,
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pll_2550,
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pll_2650,
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pll_4500,
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pll_4502,
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pll_4508,
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pll_4600,
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pll_4650,
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pll_4650c,
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pll_6552,
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pll_6552_s3c2416,
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pll_6553,
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pll_2550x,
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pll_2550xx,
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pll_2650x,
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pll_2650xx,
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pll_1417x,
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pll_1450x,
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pll_1451x,
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pll_1452x,
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pll_1460x,
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pll_0818x,
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pll_0822x,
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pll_0831x,
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pll_142xx,
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pll_0516x,
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pll_0517x,
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pll_0518x,
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};
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#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
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((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
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#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
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BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
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#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m, _p, _s, 0, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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}
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#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m, _p, _s, _k, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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}
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#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m, _p, _s - 1, 0, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.afc = (_afc), \
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}
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#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m, _p, _s, _k, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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.vsel = (_vsel), \
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}
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#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m, _p, _s, _k, 10), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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.mfr = (_mfr), \
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.mrr = (_mrr), \
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.vsel = (_vsel), \
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}
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/* NOTE: Rate table should be kept sorted in descending order. */
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struct samsung_pll_rate_table {
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unsigned int rate;
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unsigned int pdiv;
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unsigned int mdiv;
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unsigned int sdiv;
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unsigned int kdiv;
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unsigned int afc;
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unsigned int mfr;
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unsigned int mrr;
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unsigned int vsel;
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};
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#endif /* __SAMSUNG_CLK_PLL_H */
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