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39a1a8941b
Older versions of the Juno *SoC* TRM [1] recommended that the UART clock
source should be 7.2738 MHz, whereas the *system* TRM [2] stated a more
correct value of 7.3728 MHz. Somehow the wrong value managed to end up in
our DT.
Doing a prime factorisation, a modulo divide by 115200 and trying
to buy a 7.2738 MHz crystal at your favourite electronics dealer suggest
that the old value was actually a typo. The actual UART clock is driven
by a PLL, configured via a parameter in some board.txt file in the
firmware, which reads 7.37 MHz (sic!).
Fix this to correct the baud rate divisor calculation on the Juno board.
[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0515b.b/DDI0515B_b_juno_arm_development_platform_soc_trm.pdf
[2] http://infocenter.arm.com/help/topic/com.arm.doc.100113_0000_07_en/arm_versatile_express_juno_development_platform_(v2m_juno)_technical_reference_manual_100113_0000_07_en.pdf
Fixes:
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| .. | ||
| actions | ||
| al | ||
| allwinner | ||
| altera | ||
| amd | ||
| amlogic | ||
| apm | ||
| arm | ||
| bitmain | ||
| broadcom | ||
| cavium | ||
| exynos | ||
| freescale | ||
| hisilicon | ||
| intel | ||
| lg | ||
| marvell | ||
| mediatek | ||
| nvidia | ||
| qcom | ||
| realtek | ||
| renesas | ||
| rockchip | ||
| socionext | ||
| sprd | ||
| synaptics | ||
| ti | ||
| xilinx | ||
| zte | ||
| Makefile | ||