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39c5abbc54
register_intc_userimask() is called from sh4a code only. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> [r8a7779 legacy] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
39 lines
1.1 KiB
Text
39 lines
1.1 KiB
Text
config SH_INTC
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def_bool y
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select IRQ_DOMAIN
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comment "Interrupt controller options"
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config INTC_USERIMASK
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bool "Userspace interrupt masking support"
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depends on (SUPERH && CPU_SH4A) || COMPILE_TEST
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help
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This enables support for hardware-assisted userspace hardirq
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masking.
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SH-4A and newer interrupt blocks all support a special shadowed
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page with all non-masking registers obscured when mapped in to
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userspace. This is primarily for use by userspace device
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drivers that are using special priority levels.
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If in doubt, say N.
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config INTC_BALANCING
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bool "Hardware IRQ balancing support"
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depends on SMP && SUPERH && CPU_SHX3
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help
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This enables support for IRQ auto-distribution mode on SH-X3
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SMP parts. All of the balancing and CPU wakeup decisions are
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taken care of automatically by hardware for distributed
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vectors.
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If in doubt, say N.
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config INTC_MAPPING_DEBUG
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bool "Expose IRQ to per-controller id mapping via debugfs"
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depends on DEBUG_FS
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help
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This will create a debugfs entry for showing the relationship
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between system IRQs and the per-controller id tables.
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If in doubt, say N.
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