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242b1d7133
The memory controller on Tegra132 is very similar to the one found on Tegra124. But the Denver CPUs don't have an outer cache, so dcache maintenance is done slightly differently. Signed-off-by: Thierry Reding <treding@nvidia.com>
44 lines
1,023 B
C
44 lines
1,023 B
C
/*
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* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef MEMORY_TEGRA_MC_H
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#define MEMORY_TEGRA_MC_H
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#include <linux/io.h>
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#include <linux/types.h>
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#include <soc/tegra/mc.h>
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static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
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{
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return readl(mc->regs + offset);
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}
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static inline void mc_writel(struct tegra_mc *mc, u32 value,
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unsigned long offset)
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{
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writel(value, mc->regs + offset);
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}
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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extern const struct tegra_mc_soc tegra30_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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extern const struct tegra_mc_soc tegra114_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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extern const struct tegra_mc_soc tegra124_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_132_SOC
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extern const struct tegra_mc_soc tegra132_mc_soc;
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#endif
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#endif /* MEMORY_TEGRA_MC_H */
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