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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 02:39:48 +00:00
![Yijing Wang](/assets/img/avatar_default.png)
After b97ea289cf
("PCI: Assign resources before drivers claim devices
(pci_scan_root_bus())"), pci_scan_root_bus() no longer adds the devices, so
it is equivalent to mvebu_pcie_scan_bus().
Remove mvebu_pcie_scan_bus() (the hw.scan method), so we use the generic
pci_scan_root_bus() path. We also need to use pci_common_init_dev()
instead of pci_common_init() so we can supply the host bridge device
pointer.
[bhelgaas: changelog]
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
CC: Jason Cooper <jason@lakedaemon.net>
1106 lines
28 KiB
C
1106 lines
28 KiB
C
/*
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* PCIe driver for Marvell Armada 370 and Armada XP SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/mbus.h>
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#include <linux/msi.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_gpio.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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/*
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* PCIe unit register offsets.
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*/
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#define PCIE_DEV_ID_OFF 0x0000
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#define PCIE_CMD_OFF 0x0004
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#define PCIE_DEV_REV_OFF 0x0008
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#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
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#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
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#define PCIE_HEADER_LOG_4_OFF 0x0128
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#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
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#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
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#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
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#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
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#define PCIE_WIN5_CTRL_OFF 0x1880
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#define PCIE_WIN5_BASE_OFF 0x1884
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#define PCIE_WIN5_REMAP_OFF 0x188c
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#define PCIE_CONF_ADDR_OFF 0x18f8
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#define PCIE_CONF_ADDR_EN 0x80000000
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#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
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#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
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#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
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#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
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#define PCIE_CONF_ADDR(bus, devfn, where) \
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(PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
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PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
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PCIE_CONF_ADDR_EN)
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#define PCIE_CONF_DATA_OFF 0x18fc
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#define PCIE_MASK_OFF 0x1910
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#define PCIE_MASK_ENABLE_INTS 0x0f000000
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#define PCIE_CTRL_OFF 0x1a00
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#define PCIE_CTRL_X1_MODE 0x0001
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#define PCIE_STAT_OFF 0x1a04
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#define PCIE_STAT_BUS 0xff00
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#define PCIE_STAT_DEV 0x1f0000
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#define PCIE_STAT_LINK_DOWN BIT(0)
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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/* PCI configuration space of a PCI-to-PCI bridge */
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struct mvebu_sw_pci_bridge {
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u16 vendor;
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u16 device;
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u16 command;
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u16 class;
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u8 interface;
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u8 revision;
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u8 bist;
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u8 header_type;
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u8 latency_timer;
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u8 cache_line_size;
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u32 bar[2];
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u8 primary_bus;
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u8 secondary_bus;
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u8 subordinate_bus;
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u8 secondary_latency_timer;
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u8 iobase;
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u8 iolimit;
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u16 secondary_status;
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u16 membase;
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u16 memlimit;
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u16 iobaseupper;
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u16 iolimitupper;
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u8 cappointer;
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u8 reserved1;
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u16 reserved2;
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u32 romaddr;
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u8 intline;
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u8 intpin;
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u16 bridgectrl;
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};
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struct mvebu_pcie_port;
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/* Structure representing all PCIe interfaces */
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struct mvebu_pcie {
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struct platform_device *pdev;
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struct mvebu_pcie_port *ports;
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struct msi_controller *msi;
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struct resource io;
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struct resource realio;
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struct resource mem;
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struct resource busn;
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int nports;
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};
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/* Structure representing one PCIe interface */
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struct mvebu_pcie_port {
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char *name;
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void __iomem *base;
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u32 port;
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u32 lane;
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int devfn;
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unsigned int mem_target;
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unsigned int mem_attr;
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unsigned int io_target;
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unsigned int io_attr;
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struct clk *clk;
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int reset_gpio;
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int reset_active_low;
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char *reset_name;
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struct mvebu_sw_pci_bridge bridge;
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struct device_node *dn;
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struct mvebu_pcie *pcie;
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phys_addr_t memwin_base;
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size_t memwin_size;
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phys_addr_t iowin_base;
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size_t iowin_size;
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u32 saved_pcie_stat;
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};
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static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
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{
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writel(val, port->base + reg);
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}
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static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
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{
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return readl(port->base + reg);
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}
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static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
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{
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return port->io_target != -1 && port->io_attr != -1;
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}
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static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
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{
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return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
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}
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static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
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{
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u32 stat;
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stat = mvebu_readl(port, PCIE_STAT_OFF);
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stat &= ~PCIE_STAT_BUS;
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stat |= nr << 8;
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mvebu_writel(port, stat, PCIE_STAT_OFF);
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}
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static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
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{
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u32 stat;
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stat = mvebu_readl(port, PCIE_STAT_OFF);
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stat &= ~PCIE_STAT_DEV;
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stat |= nr << 16;
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mvebu_writel(port, stat, PCIE_STAT_OFF);
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}
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/*
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* Setup PCIE BARs and Address Decode Wins:
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* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
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* WIN[0-3] -> DRAM bank[0-3]
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*/
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static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
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{
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const struct mbus_dram_target_info *dram;
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u32 size;
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int i;
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dram = mv_mbus_dram_info();
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/* First, disable and clear BARs and windows. */
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for (i = 1; i < 3; i++) {
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mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
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mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
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mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
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}
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for (i = 0; i < 5; i++) {
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mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
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mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
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mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
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}
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mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
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mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
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mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
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/* Setup windows for DDR banks. Count total DDR size on the fly. */
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size = 0;
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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mvebu_writel(port, cs->base & 0xffff0000,
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PCIE_WIN04_BASE_OFF(i));
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mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
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mvebu_writel(port,
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((cs->size - 1) & 0xffff0000) |
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(cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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PCIE_WIN04_CTRL_OFF(i));
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size += cs->size;
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}
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/* Round up 'size' to the nearest power of two. */
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if ((size & (size - 1)) != 0)
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size = 1 << fls(size);
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/* Setup BAR[1] to all DRAM banks. */
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mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
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mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
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mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
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PCIE_BAR_CTRL_OFF(1));
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}
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static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
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{
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u32 cmd, mask;
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/* Point PCIe unit MBUS decode windows to DRAM space. */
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mvebu_pcie_setup_wins(port);
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/* Master + slave enable. */
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cmd = mvebu_readl(port, PCIE_CMD_OFF);
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cmd |= PCI_COMMAND_IO;
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cmd |= PCI_COMMAND_MEMORY;
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cmd |= PCI_COMMAND_MASTER;
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mvebu_writel(port, cmd, PCIE_CMD_OFF);
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/* Enable interrupt lines A-D. */
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mask = mvebu_readl(port, PCIE_MASK_OFF);
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mask |= PCIE_MASK_ENABLE_INTS;
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mvebu_writel(port, mask, PCIE_MASK_OFF);
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}
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static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
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struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val)
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{
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mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
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PCIE_CONF_ADDR_OFF);
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*val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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else if (size == 2)
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*val = (*val >> (8 * (where & 3))) & 0xffff;
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return PCIBIOS_SUCCESSFUL;
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}
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static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
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struct pci_bus *bus,
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u32 devfn, int where, int size, u32 val)
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{
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u32 _val, shift = 8 * (where & 3);
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mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
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PCIE_CONF_ADDR_OFF);
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_val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
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if (size == 4)
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_val = val;
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else if (size == 2)
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_val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
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else if (size == 1)
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_val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* Remove windows, starting from the largest ones to the smallest
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* ones.
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*/
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static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
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phys_addr_t base, size_t size)
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{
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while (size) {
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size_t sz = 1 << (fls(size) - 1);
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mvebu_mbus_del_window(base, sz);
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base += sz;
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size -= sz;
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}
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}
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/*
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* MBus windows can only have a power of two size, but PCI BARs do not
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* have this constraint. Therefore, we have to split the PCI BAR into
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* areas each having a power of two size. We start from the largest
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* one (i.e highest order bit set in the size).
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*/
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static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
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unsigned int target, unsigned int attribute,
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phys_addr_t base, size_t size,
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phys_addr_t remap)
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{
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size_t size_mapped = 0;
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while (size) {
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size_t sz = 1 << (fls(size) - 1);
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int ret;
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ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
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sz, remap);
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if (ret) {
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phys_addr_t end = base + sz - 1;
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dev_err(&port->pcie->pdev->dev,
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"Could not create MBus window at [mem %pa-%pa]: %d\n",
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&base, &end, ret);
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mvebu_pcie_del_windows(port, base - size_mapped,
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size_mapped);
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return;
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}
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size -= sz;
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size_mapped += sz;
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base += sz;
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if (remap != MVEBU_MBUS_NO_REMAP)
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remap += sz;
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}
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}
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static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
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{
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phys_addr_t iobase;
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/* Are the new iobase/iolimit values invalid? */
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if (port->bridge.iolimit < port->bridge.iobase ||
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port->bridge.iolimitupper < port->bridge.iobaseupper ||
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!(port->bridge.command & PCI_COMMAND_IO)) {
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/* If a window was configured, remove it */
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if (port->iowin_base) {
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mvebu_pcie_del_windows(port, port->iowin_base,
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port->iowin_size);
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port->iowin_base = 0;
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port->iowin_size = 0;
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}
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return;
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}
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if (!mvebu_has_ioport(port)) {
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dev_WARN(&port->pcie->pdev->dev,
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"Attempt to set IO when IO is disabled\n");
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return;
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}
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/*
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* We read the PCI-to-PCI bridge emulated registers, and
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* calculate the base address and size of the address decoding
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* window to setup, according to the PCI-to-PCI bridge
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* specifications. iobase is the bus address, port->iowin_base
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* is the CPU address.
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*/
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iobase = ((port->bridge.iobase & 0xF0) << 8) |
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(port->bridge.iobaseupper << 16);
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port->iowin_base = port->pcie->io.start + iobase;
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port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
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(port->bridge.iolimitupper << 16)) -
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iobase) + 1;
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mvebu_pcie_add_windows(port, port->io_target, port->io_attr,
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port->iowin_base, port->iowin_size,
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iobase);
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}
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static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
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{
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/* Are the new membase/memlimit values invalid? */
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if (port->bridge.memlimit < port->bridge.membase ||
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!(port->bridge.command & PCI_COMMAND_MEMORY)) {
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/* If a window was configured, remove it */
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if (port->memwin_base) {
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mvebu_pcie_del_windows(port, port->memwin_base,
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port->memwin_size);
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port->memwin_base = 0;
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port->memwin_size = 0;
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}
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return;
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}
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/*
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* We read the PCI-to-PCI bridge emulated registers, and
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* calculate the base address and size of the address decoding
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* window to setup, according to the PCI-to-PCI bridge
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* specifications.
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*/
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port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
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port->memwin_size =
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(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
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port->memwin_base + 1;
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mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,
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port->memwin_base, port->memwin_size,
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MVEBU_MBUS_NO_REMAP);
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}
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/*
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* Initialize the configuration space of the PCI-to-PCI bridge
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* associated with the given PCIe interface.
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*/
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static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
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{
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struct mvebu_sw_pci_bridge *bridge = &port->bridge;
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memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
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bridge->class = PCI_CLASS_BRIDGE_PCI;
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bridge->vendor = PCI_VENDOR_ID_MARVELL;
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bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
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bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
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bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
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bridge->cache_line_size = 0x10;
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/* We support 32 bits I/O addressing */
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bridge->iobase = PCI_IO_RANGE_TYPE_32;
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bridge->iolimit = PCI_IO_RANGE_TYPE_32;
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}
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|
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/*
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* Read the configuration space of the PCI-to-PCI bridge associated to
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* the given PCIe interface.
|
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*/
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static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
|
|
unsigned int where, int size, u32 *value)
|
|
{
|
|
struct mvebu_sw_pci_bridge *bridge = &port->bridge;
|
|
|
|
switch (where & ~3) {
|
|
case PCI_VENDOR_ID:
|
|
*value = bridge->device << 16 | bridge->vendor;
|
|
break;
|
|
|
|
case PCI_COMMAND:
|
|
*value = bridge->command;
|
|
break;
|
|
|
|
case PCI_CLASS_REVISION:
|
|
*value = bridge->class << 16 | bridge->interface << 8 |
|
|
bridge->revision;
|
|
break;
|
|
|
|
case PCI_CACHE_LINE_SIZE:
|
|
*value = bridge->bist << 24 | bridge->header_type << 16 |
|
|
bridge->latency_timer << 8 | bridge->cache_line_size;
|
|
break;
|
|
|
|
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
|
|
*value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
|
|
break;
|
|
|
|
case PCI_PRIMARY_BUS:
|
|
*value = (bridge->secondary_latency_timer << 24 |
|
|
bridge->subordinate_bus << 16 |
|
|
bridge->secondary_bus << 8 |
|
|
bridge->primary_bus);
|
|
break;
|
|
|
|
case PCI_IO_BASE:
|
|
if (!mvebu_has_ioport(port))
|
|
*value = bridge->secondary_status << 16;
|
|
else
|
|
*value = (bridge->secondary_status << 16 |
|
|
bridge->iolimit << 8 |
|
|
bridge->iobase);
|
|
break;
|
|
|
|
case PCI_MEMORY_BASE:
|
|
*value = (bridge->memlimit << 16 | bridge->membase);
|
|
break;
|
|
|
|
case PCI_PREF_MEMORY_BASE:
|
|
*value = 0;
|
|
break;
|
|
|
|
case PCI_IO_BASE_UPPER16:
|
|
*value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
|
|
break;
|
|
|
|
case PCI_ROM_ADDRESS1:
|
|
*value = 0;
|
|
break;
|
|
|
|
case PCI_INTERRUPT_LINE:
|
|
/* LINE PIN MIN_GNT MAX_LAT */
|
|
*value = 0;
|
|
break;
|
|
|
|
default:
|
|
*value = 0xffffffff;
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
}
|
|
|
|
if (size == 2)
|
|
*value = (*value >> (8 * (where & 3))) & 0xffff;
|
|
else if (size == 1)
|
|
*value = (*value >> (8 * (where & 3))) & 0xff;
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
/* Write to the PCI-to-PCI bridge configuration space */
|
|
static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
|
|
unsigned int where, int size, u32 value)
|
|
{
|
|
struct mvebu_sw_pci_bridge *bridge = &port->bridge;
|
|
u32 mask, reg;
|
|
int err;
|
|
|
|
if (size == 4)
|
|
mask = 0x0;
|
|
else if (size == 2)
|
|
mask = ~(0xffff << ((where & 3) * 8));
|
|
else if (size == 1)
|
|
mask = ~(0xff << ((where & 3) * 8));
|
|
else
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
value = (reg & mask) | value << ((where & 3) * 8);
|
|
|
|
switch (where & ~3) {
|
|
case PCI_COMMAND:
|
|
{
|
|
u32 old = bridge->command;
|
|
|
|
if (!mvebu_has_ioport(port))
|
|
value &= ~PCI_COMMAND_IO;
|
|
|
|
bridge->command = value & 0xffff;
|
|
if ((old ^ bridge->command) & PCI_COMMAND_IO)
|
|
mvebu_pcie_handle_iobase_change(port);
|
|
if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
|
|
mvebu_pcie_handle_membase_change(port);
|
|
break;
|
|
}
|
|
|
|
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
|
|
bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
|
|
break;
|
|
|
|
case PCI_IO_BASE:
|
|
/*
|
|
* We also keep bit 1 set, it is a read-only bit that
|
|
* indicates we support 32 bits addressing for the
|
|
* I/O
|
|
*/
|
|
bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
|
|
bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
|
|
mvebu_pcie_handle_iobase_change(port);
|
|
break;
|
|
|
|
case PCI_MEMORY_BASE:
|
|
bridge->membase = value & 0xffff;
|
|
bridge->memlimit = value >> 16;
|
|
mvebu_pcie_handle_membase_change(port);
|
|
break;
|
|
|
|
case PCI_IO_BASE_UPPER16:
|
|
bridge->iobaseupper = value & 0xffff;
|
|
bridge->iolimitupper = value >> 16;
|
|
mvebu_pcie_handle_iobase_change(port);
|
|
break;
|
|
|
|
case PCI_PRIMARY_BUS:
|
|
bridge->primary_bus = value & 0xff;
|
|
bridge->secondary_bus = (value >> 8) & 0xff;
|
|
bridge->subordinate_bus = (value >> 16) & 0xff;
|
|
bridge->secondary_latency_timer = (value >> 24) & 0xff;
|
|
mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
|
|
{
|
|
return sys->private_data;
|
|
}
|
|
|
|
static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
|
|
struct pci_bus *bus,
|
|
int devfn)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
struct mvebu_pcie_port *port = &pcie->ports[i];
|
|
|
|
if (bus->number == 0 && port->devfn == devfn)
|
|
return port;
|
|
if (bus->number != 0 &&
|
|
bus->number >= port->bridge.secondary_bus &&
|
|
bus->number <= port->bridge.subordinate_bus)
|
|
return port;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/* PCI configuration space write function */
|
|
static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
|
int where, int size, u32 val)
|
|
{
|
|
struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
|
|
struct mvebu_pcie_port *port;
|
|
int ret;
|
|
|
|
port = mvebu_pcie_find_port(pcie, bus, devfn);
|
|
if (!port)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
/* Access the emulated PCI-to-PCI bridge */
|
|
if (bus->number == 0)
|
|
return mvebu_sw_pci_bridge_write(port, where, size, val);
|
|
|
|
if (!mvebu_pcie_link_up(port))
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
/*
|
|
* On the secondary bus, we don't want to expose any other
|
|
* device than the device physically connected in the PCIe
|
|
* slot, visible in slot 0. In slot 1, there's a special
|
|
* Marvell device that only makes sense when the Armada is
|
|
* used as a PCIe endpoint.
|
|
*/
|
|
if (bus->number == port->bridge.secondary_bus &&
|
|
PCI_SLOT(devfn) != 0)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
/* Access the real PCIe interface */
|
|
ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
|
|
where, size, val);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* PCI configuration space read function */
|
|
static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
|
int size, u32 *val)
|
|
{
|
|
struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
|
|
struct mvebu_pcie_port *port;
|
|
int ret;
|
|
|
|
port = mvebu_pcie_find_port(pcie, bus, devfn);
|
|
if (!port) {
|
|
*val = 0xffffffff;
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
/* Access the emulated PCI-to-PCI bridge */
|
|
if (bus->number == 0)
|
|
return mvebu_sw_pci_bridge_read(port, where, size, val);
|
|
|
|
if (!mvebu_pcie_link_up(port)) {
|
|
*val = 0xffffffff;
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
/*
|
|
* On the secondary bus, we don't want to expose any other
|
|
* device than the device physically connected in the PCIe
|
|
* slot, visible in slot 0. In slot 1, there's a special
|
|
* Marvell device that only makes sense when the Armada is
|
|
* used as a PCIe endpoint.
|
|
*/
|
|
if (bus->number == port->bridge.secondary_bus &&
|
|
PCI_SLOT(devfn) != 0) {
|
|
*val = 0xffffffff;
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
/* Access the real PCIe interface */
|
|
ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
|
|
where, size, val);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct pci_ops mvebu_pcie_ops = {
|
|
.read = mvebu_pcie_rd_conf,
|
|
.write = mvebu_pcie_wr_conf,
|
|
};
|
|
|
|
static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
|
|
{
|
|
struct mvebu_pcie *pcie = sys_to_pcie(sys);
|
|
int i;
|
|
|
|
pcie->mem.name = "PCI MEM";
|
|
pcie->realio.name = "PCI I/O";
|
|
|
|
if (request_resource(&iomem_resource, &pcie->mem))
|
|
return 0;
|
|
|
|
if (resource_size(&pcie->realio) != 0) {
|
|
if (request_resource(&ioport_resource, &pcie->realio)) {
|
|
release_resource(&pcie->mem);
|
|
return 0;
|
|
}
|
|
pci_add_resource_offset(&sys->resources, &pcie->realio,
|
|
sys->io_offset);
|
|
}
|
|
pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
|
|
pci_add_resource(&sys->resources, &pcie->busn);
|
|
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
struct mvebu_pcie_port *port = &pcie->ports[i];
|
|
|
|
if (!port->base)
|
|
continue;
|
|
mvebu_pcie_setup_hw(port);
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
|
|
const struct resource *res,
|
|
resource_size_t start,
|
|
resource_size_t size,
|
|
resource_size_t align)
|
|
{
|
|
if (dev->bus->number != 0)
|
|
return start;
|
|
|
|
/*
|
|
* On the PCI-to-PCI bridge side, the I/O windows must have at
|
|
* least a 64 KB size and the memory windows must have at
|
|
* least a 1 MB size. Moreover, MBus windows need to have a
|
|
* base address aligned on their size, and their size must be
|
|
* a power of two. This means that if the BAR doesn't have a
|
|
* power of two size, several MBus windows will actually be
|
|
* created. We need to ensure that the biggest MBus window
|
|
* (which will be the first one) is aligned on its size, which
|
|
* explains the rounddown_pow_of_two() being done here.
|
|
*/
|
|
if (res->flags & IORESOURCE_IO)
|
|
return round_up(start, max_t(resource_size_t, SZ_64K,
|
|
rounddown_pow_of_two(size)));
|
|
else if (res->flags & IORESOURCE_MEM)
|
|
return round_up(start, max_t(resource_size_t, SZ_1M,
|
|
rounddown_pow_of_two(size)));
|
|
else
|
|
return start;
|
|
}
|
|
|
|
static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
|
|
{
|
|
struct hw_pci hw;
|
|
|
|
memset(&hw, 0, sizeof(hw));
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
hw.msi_ctrl = pcie->msi;
|
|
#endif
|
|
|
|
hw.nr_controllers = 1;
|
|
hw.private_data = (void **)&pcie;
|
|
hw.setup = mvebu_pcie_setup;
|
|
hw.map_irq = of_irq_parse_and_map_pci;
|
|
hw.ops = &mvebu_pcie_ops;
|
|
hw.align_resource = mvebu_pcie_align_resource;
|
|
|
|
pci_common_init_dev(&pcie->pdev->dev, &hw);
|
|
}
|
|
|
|
/*
|
|
* Looks up the list of register addresses encoded into the reg =
|
|
* <...> property for one that matches the given port/lane. Once
|
|
* found, maps it.
|
|
*/
|
|
static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
|
|
struct device_node *np,
|
|
struct mvebu_pcie_port *port)
|
|
{
|
|
struct resource regs;
|
|
int ret = 0;
|
|
|
|
ret = of_address_to_resource(np, 0, ®s);
|
|
if (ret)
|
|
return ERR_PTR(ret);
|
|
|
|
return devm_ioremap_resource(&pdev->dev, ®s);
|
|
}
|
|
|
|
#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
|
|
#define DT_TYPE_IO 0x1
|
|
#define DT_TYPE_MEM32 0x2
|
|
#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
|
|
#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
|
|
|
|
static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
|
|
unsigned long type,
|
|
unsigned int *tgt,
|
|
unsigned int *attr)
|
|
{
|
|
const int na = 3, ns = 2;
|
|
const __be32 *range;
|
|
int rlen, nranges, rangesz, pna, i;
|
|
|
|
*tgt = -1;
|
|
*attr = -1;
|
|
|
|
range = of_get_property(np, "ranges", &rlen);
|
|
if (!range)
|
|
return -EINVAL;
|
|
|
|
pna = of_n_addr_cells(np);
|
|
rangesz = pna + na + ns;
|
|
nranges = rlen / sizeof(__be32) / rangesz;
|
|
|
|
for (i = 0; i < nranges; i++, range += rangesz) {
|
|
u32 flags = of_read_number(range, 1);
|
|
u32 slot = of_read_number(range + 1, 1);
|
|
u64 cpuaddr = of_read_number(range + na, pna);
|
|
unsigned long rtype;
|
|
|
|
if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
|
|
rtype = IORESOURCE_IO;
|
|
else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
|
|
rtype = IORESOURCE_MEM;
|
|
else
|
|
continue;
|
|
|
|
if (slot == PCI_SLOT(devfn) && type == rtype) {
|
|
*tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
|
|
*attr = DT_CPUADDR_TO_ATTR(cpuaddr);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return -ENOENT;
|
|
}
|
|
|
|
static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
|
|
{
|
|
struct device_node *msi_node;
|
|
|
|
msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
|
|
"msi-parent", 0);
|
|
if (!msi_node)
|
|
return;
|
|
|
|
pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
|
|
|
|
if (pcie->msi)
|
|
pcie->msi->dev = &pcie->pdev->dev;
|
|
}
|
|
|
|
static int mvebu_pcie_suspend(struct device *dev)
|
|
{
|
|
struct mvebu_pcie *pcie;
|
|
int i;
|
|
|
|
pcie = dev_get_drvdata(dev);
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
struct mvebu_pcie_port *port = pcie->ports + i;
|
|
port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mvebu_pcie_resume(struct device *dev)
|
|
{
|
|
struct mvebu_pcie *pcie;
|
|
int i;
|
|
|
|
pcie = dev_get_drvdata(dev);
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
struct mvebu_pcie_port *port = pcie->ports + i;
|
|
mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
|
|
mvebu_pcie_setup_hw(port);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mvebu_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct mvebu_pcie *pcie;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct device_node *child;
|
|
int i, ret;
|
|
|
|
pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
|
|
GFP_KERNEL);
|
|
if (!pcie)
|
|
return -ENOMEM;
|
|
|
|
pcie->pdev = pdev;
|
|
platform_set_drvdata(pdev, pcie);
|
|
|
|
/* Get the PCIe memory and I/O aperture */
|
|
mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
|
|
if (resource_size(&pcie->mem) == 0) {
|
|
dev_err(&pdev->dev, "invalid memory aperture size\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
mvebu_mbus_get_pcie_io_aperture(&pcie->io);
|
|
|
|
if (resource_size(&pcie->io) != 0) {
|
|
pcie->realio.flags = pcie->io.flags;
|
|
pcie->realio.start = PCIBIOS_MIN_IO;
|
|
pcie->realio.end = min_t(resource_size_t,
|
|
IO_SPACE_LIMIT,
|
|
resource_size(&pcie->io));
|
|
} else
|
|
pcie->realio = pcie->io;
|
|
|
|
/* Get the bus range */
|
|
ret = of_pci_parse_bus_range(np, &pcie->busn);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
i = 0;
|
|
for_each_child_of_node(pdev->dev.of_node, child) {
|
|
if (!of_device_is_available(child))
|
|
continue;
|
|
i++;
|
|
}
|
|
|
|
pcie->ports = devm_kzalloc(&pdev->dev, i *
|
|
sizeof(struct mvebu_pcie_port),
|
|
GFP_KERNEL);
|
|
if (!pcie->ports)
|
|
return -ENOMEM;
|
|
|
|
i = 0;
|
|
for_each_child_of_node(pdev->dev.of_node, child) {
|
|
struct mvebu_pcie_port *port = &pcie->ports[i];
|
|
enum of_gpio_flags flags;
|
|
|
|
if (!of_device_is_available(child))
|
|
continue;
|
|
|
|
port->pcie = pcie;
|
|
|
|
if (of_property_read_u32(child, "marvell,pcie-port",
|
|
&port->port)) {
|
|
dev_warn(&pdev->dev,
|
|
"ignoring PCIe DT node, missing pcie-port property\n");
|
|
continue;
|
|
}
|
|
|
|
if (of_property_read_u32(child, "marvell,pcie-lane",
|
|
&port->lane))
|
|
port->lane = 0;
|
|
|
|
port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
|
|
port->port, port->lane);
|
|
|
|
port->devfn = of_pci_get_devfn(child);
|
|
if (port->devfn < 0)
|
|
continue;
|
|
|
|
ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
|
|
&port->mem_target, &port->mem_attr);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
|
|
port->port, port->lane);
|
|
continue;
|
|
}
|
|
|
|
if (resource_size(&pcie->io) != 0)
|
|
mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
|
|
&port->io_target, &port->io_attr);
|
|
else {
|
|
port->io_target = -1;
|
|
port->io_attr = -1;
|
|
}
|
|
|
|
port->reset_gpio = of_get_named_gpio_flags(child,
|
|
"reset-gpios", 0, &flags);
|
|
if (gpio_is_valid(port->reset_gpio)) {
|
|
u32 reset_udelay = 20000;
|
|
|
|
port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
|
|
port->reset_name = kasprintf(GFP_KERNEL,
|
|
"pcie%d.%d-reset", port->port, port->lane);
|
|
of_property_read_u32(child, "reset-delay-us",
|
|
&reset_udelay);
|
|
|
|
ret = devm_gpio_request_one(&pdev->dev,
|
|
port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
|
|
if (ret) {
|
|
if (ret == -EPROBE_DEFER)
|
|
return ret;
|
|
continue;
|
|
}
|
|
|
|
gpio_set_value(port->reset_gpio,
|
|
(port->reset_active_low) ? 1 : 0);
|
|
msleep(reset_udelay/1000);
|
|
}
|
|
|
|
port->clk = of_clk_get_by_name(child, NULL);
|
|
if (IS_ERR(port->clk)) {
|
|
dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
|
|
port->port, port->lane);
|
|
continue;
|
|
}
|
|
|
|
ret = clk_prepare_enable(port->clk);
|
|
if (ret)
|
|
continue;
|
|
|
|
port->base = mvebu_pcie_map_registers(pdev, child, port);
|
|
if (IS_ERR(port->base)) {
|
|
dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
|
|
port->port, port->lane);
|
|
port->base = NULL;
|
|
clk_disable_unprepare(port->clk);
|
|
continue;
|
|
}
|
|
|
|
mvebu_pcie_set_local_dev_nr(port, 1);
|
|
|
|
port->dn = child;
|
|
mvebu_sw_pci_bridge_init(port);
|
|
i++;
|
|
}
|
|
|
|
pcie->nports = i;
|
|
|
|
for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
|
|
pci_ioremap_io(i, pcie->io.start + i);
|
|
|
|
mvebu_pcie_msi_enable(pcie);
|
|
mvebu_pcie_enable(pcie);
|
|
|
|
platform_set_drvdata(pdev, pcie);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mvebu_pcie_of_match_table[] = {
|
|
{ .compatible = "marvell,armada-xp-pcie", },
|
|
{ .compatible = "marvell,armada-370-pcie", },
|
|
{ .compatible = "marvell,dove-pcie", },
|
|
{ .compatible = "marvell,kirkwood-pcie", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
|
|
|
|
static struct dev_pm_ops mvebu_pcie_pm_ops = {
|
|
.suspend_noirq = mvebu_pcie_suspend,
|
|
.resume_noirq = mvebu_pcie_resume,
|
|
};
|
|
|
|
static struct platform_driver mvebu_pcie_driver = {
|
|
.driver = {
|
|
.name = "mvebu-pcie",
|
|
.of_match_table = mvebu_pcie_of_match_table,
|
|
/* driver unloading/unbinding currently not supported */
|
|
.suppress_bind_attrs = true,
|
|
.pm = &mvebu_pcie_pm_ops,
|
|
},
|
|
.probe = mvebu_pcie_probe,
|
|
};
|
|
module_platform_driver(mvebu_pcie_driver);
|
|
|
|
MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
|
|
MODULE_DESCRIPTION("Marvell EBU PCIe driver");
|
|
MODULE_LICENSE("GPL v2");
|