mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 10:49:33 +00:00
![Linus Torvalds](/assets/img/avatar_default.png)
- Rework of the core ACPI resources parsing code to fix issues in it and make using resource offsets more convenient and consolidation of some resource-handing code in a couple of places that have grown analagous data structures and code to cover the the same gap in the core (Jiang Liu, Thomas Gleixner, Lv Zheng). - ACPI-based IOAPIC hotplug support on top of the resources handling rework (Jiang Liu, Yinghai Lu). - ACPICA update to upstream release 20150204 including an interrupt handling rework that allows drivers to install raw handlers for ACPI GPEs which then become entirely responsible for the given GPE and the ACPICA core code won't touch it (Lv Zheng, David E Box, Octavian Purdila). - ACPI EC driver rework to fix several concurrency issues and other problems related to events handling on top of the ACPICA's new support for raw GPE handlers (Lv Zheng). - New ACPI driver for AMD SoCs analogous to the LPSS (Low-Power Subsystem) driver for Intel chips (Ken Xue). - Two minor fixes of the ACPI LPSS driver (Heikki Krogerus, Jarkko Nikula). - Two new blacklist entries for machines (Samsung 730U3E/740U3E and 510R) where the native backlight interface doesn't work correctly while the ACPI one does (Hans de Goede). - Rework of the ACPI processor driver's handling of idle states to make the code more straightforward and less bloated overall (Rafael J Wysocki). - Assorted minor fixes related to ACPI and SFI (Andreas Ruprecht, Andy Shevchenko, Hanjun Guo, Jan Beulich, Rafael J Wysocki, Yaowei Bai). - PCI core power management modification to avoid resuming (some) runtime-suspended devices during system suspend if they are in the right states already (Rafael J Wysocki). - New SFI-based cpufreq driver for Intel platforms using SFI (Srinidhi Kasagar). - cpufreq core fixes, cleanups and simplifications (Viresh Kumar, Doug Anderson, Wolfram Sang). - SkyLake CPU support and other updates for the intel_pstate driver (Kristen Carlson Accardi, Srinivas Pandruvada). - cpufreq-dt driver cleanup (Markus Elfring). - Init fix for the ARM big.LITTLE cpuidle driver (Sudeep Holla). - Generic power domains core code fixes and cleanups (Ulf Hansson). - Operating Performance Points (OPP) core code cleanups and kernel documentation update (Nishanth Menon). - New dabugfs interface to make the list of PM QoS constraints available to user space (Nishanth Menon). - New devfreq driver for Tegra Activity Monitor (Tomeu Vizoso). - New devfreq class (devfreq_event) to provide raw utilization data to devfreq governors (Chanwoo Choi). - Assorted minor fixes and cleanups related to power management (Andreas Ruprecht, Krzysztof Kozlowski, Rickard Strandqvist, Pavel Machek, Todd E Brandt, Wonhong Kwon). - turbostat updates (Len Brown) and cpupower Makefile improvement (Sriram Raghunathan). / -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABCAAGBQJU2neOAAoJEILEb/54YlRx51QP/jrv1Wb5eMaemzMksPIWI5Zn I8IbxzToxu7wDDsrTBRv+LuyllMPrnppFOHHvB35gUYu7Y6I066s3ErwuqeFlbmy +VicmyGMahv3yN74qg49MXzWtaJZa8hrFXn8ItujiUIcs08yELi0vBQFlZImIbTB PdQngO88VfiOVjDvmKkYUU//9Sc9LCU0ZcdUQXSnA1oNOxuUHjiARz98R03hhSqu BWR+7M0uaFbu6XeK+BExMXJTpKicIBZ1GAF6hWrS8V4aYg+hH1cwjf2neDAzZkcU UkXieJlLJrCq+ZBNcy7WEhkWQkqJNWei5WYiy6eoQeQpNoliY2V+2OtSMJaKqDye PIiMwXstyDc5rgyULN0d1UUzY6mbcUt2rOL0VN2bsFVIJ1HWCq8mr8qq689pQUYv tcH18VQ2/6r2zW28sTO/ByWLYomklD/Y6bw2onMhGx3Knl0D8xYJKapVnTGhr5eY d4k41ybHSWNKfXsZxdJc+RxndhPwj9rFLfvY/CZEhLcW+2pAiMarRDOPXDoUI7/l aJpmPzy/6mPXGBnTfr6jKDSY3gXNazRIvfPbAdiGayKcHcdRM4glbSbNH0/h1Iq6 HKa8v9Fx87k1X5r4ZbhiPdABWlxuKDiM7725rfGpvjlWC3GNFOq7YTVMOuuBA225 Mu9PRZbOsZsnyNkixBpX =zZER -----END PGP SIGNATURE----- Merge tag 'pm+acpi-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull ACPI and power management updates from Rafael Wysocki: "We have a few new features this time, including a new SFI-based cpufreq driver, a new devfreq driver for Tegra Activity Monitor, a new devfreq class for providing its governors with raw utilization data and a new ACPI driver for AMD SoCs. Still, the majority of changes here are reworks of existing code to make it more straightforward or to prepare it for implementing new features on top of it. The primary example is the rework of ACPI resources handling from Jiang Liu, Thomas Gleixner and Lv Zheng with support for IOAPIC hotplug implemented on top of it, but there is quite a number of changes of this kind in the cpufreq core, ACPICA, ACPI EC driver, ACPI processor driver and the generic power domains core code too. The most active developer is Viresh Kumar with his cpufreq changes. Specifics: - Rework of the core ACPI resources parsing code to fix issues in it and make using resource offsets more convenient and consolidation of some resource-handing code in a couple of places that have grown analagous data structures and code to cover the the same gap in the core (Jiang Liu, Thomas Gleixner, Lv Zheng). - ACPI-based IOAPIC hotplug support on top of the resources handling rework (Jiang Liu, Yinghai Lu). - ACPICA update to upstream release 20150204 including an interrupt handling rework that allows drivers to install raw handlers for ACPI GPEs which then become entirely responsible for the given GPE and the ACPICA core code won't touch it (Lv Zheng, David E Box, Octavian Purdila). - ACPI EC driver rework to fix several concurrency issues and other problems related to events handling on top of the ACPICA's new support for raw GPE handlers (Lv Zheng). - New ACPI driver for AMD SoCs analogous to the LPSS (Low-Power Subsystem) driver for Intel chips (Ken Xue). - Two minor fixes of the ACPI LPSS driver (Heikki Krogerus, Jarkko Nikula). - Two new blacklist entries for machines (Samsung 730U3E/740U3E and 510R) where the native backlight interface doesn't work correctly while the ACPI one does (Hans de Goede). - Rework of the ACPI processor driver's handling of idle states to make the code more straightforward and less bloated overall (Rafael J Wysocki). - Assorted minor fixes related to ACPI and SFI (Andreas Ruprecht, Andy Shevchenko, Hanjun Guo, Jan Beulich, Rafael J Wysocki, Yaowei Bai). - PCI core power management modification to avoid resuming (some) runtime-suspended devices during system suspend if they are in the right states already (Rafael J Wysocki). - New SFI-based cpufreq driver for Intel platforms using SFI (Srinidhi Kasagar). - cpufreq core fixes, cleanups and simplifications (Viresh Kumar, Doug Anderson, Wolfram Sang). - SkyLake CPU support and other updates for the intel_pstate driver (Kristen Carlson Accardi, Srinivas Pandruvada). - cpufreq-dt driver cleanup (Markus Elfring). - Init fix for the ARM big.LITTLE cpuidle driver (Sudeep Holla). - Generic power domains core code fixes and cleanups (Ulf Hansson). - Operating Performance Points (OPP) core code cleanups and kernel documentation update (Nishanth Menon). - New dabugfs interface to make the list of PM QoS constraints available to user space (Nishanth Menon). - New devfreq driver for Tegra Activity Monitor (Tomeu Vizoso). - New devfreq class (devfreq_event) to provide raw utilization data to devfreq governors (Chanwoo Choi). - Assorted minor fixes and cleanups related to power management (Andreas Ruprecht, Krzysztof Kozlowski, Rickard Strandqvist, Pavel Machek, Todd E Brandt, Wonhong Kwon). - turbostat updates (Len Brown) and cpupower Makefile improvement (Sriram Raghunathan)" * tag 'pm+acpi-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (151 commits) tools/power turbostat: relax dependency on APERF_MSR tools/power turbostat: relax dependency on invariant TSC Merge branch 'pci/host-generic' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci into acpi-resources tools/power turbostat: decode MSR_*_PERF_LIMIT_REASONS tools/power turbostat: relax dependency on root permission ACPI / video: Add disable_native_backlight quirk for Samsung 510R ACPI / PM: Remove unneeded nested #ifdef USB / PM: Remove unneeded #ifdef and associated dead code intel_pstate: provide option to only use intel_pstate with HWP ACPI / EC: Add GPE reference counting debugging messages ACPI / EC: Add query flushing support ACPI / EC: Refine command storm prevention support ACPI / EC: Add command flushing support. ACPI / EC: Introduce STARTED/STOPPED flags to replace BLOCKED flag ACPI: add AMD ACPI2Platform device support for x86 system ACPI / table: remove duplicate NULL check for the handler of acpi_table_parse() ACPI / EC: Update revision due to raw handler mode. ACPI / EC: Reduce ec_poll() by referencing the last register access timestamp. ACPI / EC: Fix several GPE handling issues by deploying ACPI_GPE_DISPATCH_RAW_HANDLER mode. ACPICA: Events: Enable APIs to allow interrupt/polling adaptive request based GPE handling model ...
890 lines
22 KiB
C
890 lines
22 KiB
C
/*
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* PCIe host controller driver for Xilinx AXI PCIe Bridge
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*
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* Copyright (c) 2012 - 2014 Xilinx, Inc.
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*
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* Based on the Tegra PCIe driver
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*
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* Bits taken from Synopsys Designware Host controller driver and
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* ARM PCI Host generic driver.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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/* Register definitions */
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#define XILINX_PCIE_REG_BIR 0x00000130
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#define XILINX_PCIE_REG_IDR 0x00000138
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#define XILINX_PCIE_REG_IMR 0x0000013c
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#define XILINX_PCIE_REG_PSCR 0x00000144
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#define XILINX_PCIE_REG_RPSC 0x00000148
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#define XILINX_PCIE_REG_MSIBASE1 0x0000014c
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#define XILINX_PCIE_REG_MSIBASE2 0x00000150
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#define XILINX_PCIE_REG_RPEFR 0x00000154
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#define XILINX_PCIE_REG_RPIFR1 0x00000158
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#define XILINX_PCIE_REG_RPIFR2 0x0000015c
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/* Interrupt registers definitions */
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#define XILINX_PCIE_INTR_LINK_DOWN BIT(0)
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#define XILINX_PCIE_INTR_ECRC_ERR BIT(1)
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#define XILINX_PCIE_INTR_STR_ERR BIT(2)
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#define XILINX_PCIE_INTR_HOT_RESET BIT(3)
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#define XILINX_PCIE_INTR_CFG_TIMEOUT BIT(8)
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#define XILINX_PCIE_INTR_CORRECTABLE BIT(9)
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#define XILINX_PCIE_INTR_NONFATAL BIT(10)
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#define XILINX_PCIE_INTR_FATAL BIT(11)
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#define XILINX_PCIE_INTR_INTX BIT(16)
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#define XILINX_PCIE_INTR_MSI BIT(17)
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#define XILINX_PCIE_INTR_SLV_UNSUPP BIT(20)
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#define XILINX_PCIE_INTR_SLV_UNEXP BIT(21)
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#define XILINX_PCIE_INTR_SLV_COMPL BIT(22)
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#define XILINX_PCIE_INTR_SLV_ERRP BIT(23)
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#define XILINX_PCIE_INTR_SLV_CMPABT BIT(24)
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#define XILINX_PCIE_INTR_SLV_ILLBUR BIT(25)
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#define XILINX_PCIE_INTR_MST_DECERR BIT(26)
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#define XILINX_PCIE_INTR_MST_SLVERR BIT(27)
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#define XILINX_PCIE_INTR_MST_ERRP BIT(28)
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#define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED
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#define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF
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/* Root Port Error FIFO Read Register definitions */
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#define XILINX_PCIE_RPEFR_ERR_VALID BIT(18)
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#define XILINX_PCIE_RPEFR_REQ_ID GENMASK(15, 0)
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#define XILINX_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF
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/* Root Port Interrupt FIFO Read Register 1 definitions */
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#define XILINX_PCIE_RPIFR1_INTR_VALID BIT(31)
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#define XILINX_PCIE_RPIFR1_MSI_INTR BIT(30)
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#define XILINX_PCIE_RPIFR1_INTR_MASK GENMASK(28, 27)
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#define XILINX_PCIE_RPIFR1_ALL_MASK 0xFFFFFFFF
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#define XILINX_PCIE_RPIFR1_INTR_SHIFT 27
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/* Bridge Info Register definitions */
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#define XILINX_PCIE_BIR_ECAM_SZ_MASK GENMASK(18, 16)
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#define XILINX_PCIE_BIR_ECAM_SZ_SHIFT 16
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/* Root Port Interrupt FIFO Read Register 2 definitions */
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#define XILINX_PCIE_RPIFR2_MSG_DATA GENMASK(15, 0)
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/* Root Port Status/control Register definitions */
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#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
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/* Phy Status/Control Register definitions */
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#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
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/* ECAM definitions */
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#define ECAM_BUS_NUM_SHIFT 20
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#define ECAM_DEV_NUM_SHIFT 12
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/* Number of MSI IRQs */
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#define XILINX_NUM_MSI_IRQS 128
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/* Number of Memory Resources */
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#define XILINX_MAX_NUM_RESOURCES 3
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/**
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* struct xilinx_pcie_port - PCIe port information
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* @reg_base: IO Mapped Register Base
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* @irq: Interrupt number
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* @msi_pages: MSI pages
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* @root_busno: Root Bus number
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* @dev: Device pointer
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* @irq_domain: IRQ domain pointer
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* @bus_range: Bus range
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* @resources: Bus Resources
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*/
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struct xilinx_pcie_port {
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void __iomem *reg_base;
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u32 irq;
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unsigned long msi_pages;
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u8 root_busno;
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struct device *dev;
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struct irq_domain *irq_domain;
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struct resource bus_range;
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struct list_head resources;
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};
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static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
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static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys)
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{
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return sys->private_data;
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}
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static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
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{
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return readl(port->reg_base + reg);
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}
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static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg)
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{
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writel(val, port->reg_base + reg);
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}
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static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
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{
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return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
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XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
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}
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/**
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* xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
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* @port: PCIe port information
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*/
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static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
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{
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unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
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if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
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dev_dbg(port->dev, "Requester ID %lu\n",
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val & XILINX_PCIE_RPEFR_REQ_ID);
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pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
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XILINX_PCIE_REG_RPEFR);
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}
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}
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/**
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* xilinx_pcie_valid_device - Check if a valid device is present on bus
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* @bus: PCI Bus structure
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* @devfn: device/function
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*
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* Return: 'true' on success and 'false' if invalid device is found
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*/
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static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
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{
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struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
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/* Check if link is up when trying to access downstream ports */
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if (bus->number != port->root_busno)
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if (!xilinx_pcie_link_is_up(port))
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return false;
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/* Only one device down on each root port */
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if (bus->number == port->root_busno && devfn > 0)
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return false;
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/*
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* Do not read more than one device on the bus directly attached
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* to RC.
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*/
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if (bus->primary == port->root_busno && devfn > 0)
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return false;
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return true;
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}
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/**
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* xilinx_pcie_map_bus - Get configuration base
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* @bus: PCI Bus structure
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* @devfn: Device/function
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* @where: Offset from base
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*
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* Return: Base address of the configuration space needed to be
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* accessed.
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*/
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static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
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int relbus;
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if (!xilinx_pcie_valid_device(bus, devfn))
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return NULL;
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relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
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(devfn << ECAM_DEV_NUM_SHIFT);
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return port->reg_base + relbus + where;
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}
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/* PCIe operations */
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static struct pci_ops xilinx_pcie_ops = {
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.map_bus = xilinx_pcie_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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/* MSI functions */
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/**
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* xilinx_pcie_destroy_msi - Free MSI number
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* @irq: IRQ to be freed
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*/
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static void xilinx_pcie_destroy_msi(unsigned int irq)
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{
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struct irq_desc *desc;
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struct msi_desc *msi;
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struct xilinx_pcie_port *port;
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desc = irq_to_desc(irq);
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msi = irq_desc_get_msi_desc(desc);
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port = sys_to_pcie(msi->dev->bus->sysdata);
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if (!test_bit(irq, msi_irq_in_use))
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dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
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else
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clear_bit(irq, msi_irq_in_use);
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}
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/**
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* xilinx_pcie_assign_msi - Allocate MSI number
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* @port: PCIe port structure
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*
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* Return: A valid IRQ on success and error value on failure.
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*/
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static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
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{
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int pos;
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pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
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if (pos < XILINX_NUM_MSI_IRQS)
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set_bit(pos, msi_irq_in_use);
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else
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return -ENOSPC;
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return pos;
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}
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/**
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* xilinx_msi_teardown_irq - Destroy the MSI
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* @chip: MSI Chip descriptor
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* @irq: MSI IRQ to destroy
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*/
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static void xilinx_msi_teardown_irq(struct msi_controller *chip,
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unsigned int irq)
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{
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xilinx_pcie_destroy_msi(irq);
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}
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/**
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* xilinx_pcie_msi_setup_irq - Setup MSI request
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* @chip: MSI chip pointer
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* @pdev: PCIe device pointer
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* @desc: MSI descriptor pointer
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*
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* Return: '0' on success and error value on failure
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*/
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static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
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struct pci_dev *pdev,
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struct msi_desc *desc)
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{
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struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata);
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unsigned int irq;
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int hwirq;
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struct msi_msg msg;
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phys_addr_t msg_addr;
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hwirq = xilinx_pcie_assign_msi(port);
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if (hwirq < 0)
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return hwirq;
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irq = irq_create_mapping(port->irq_domain, hwirq);
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if (!irq)
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return -EINVAL;
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irq_set_msi_desc(irq, desc);
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msg_addr = virt_to_phys((void *)port->msi_pages);
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msg.address_hi = 0;
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msg.address_lo = msg_addr;
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msg.data = irq;
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pci_write_msi_msg(irq, &msg);
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return 0;
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}
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|
|
|
/* MSI Chip Descriptor */
|
|
static struct msi_controller xilinx_pcie_msi_chip = {
|
|
.setup_irq = xilinx_pcie_msi_setup_irq,
|
|
.teardown_irq = xilinx_msi_teardown_irq,
|
|
};
|
|
|
|
/* HW Interrupt Chip Descriptor */
|
|
static struct irq_chip xilinx_msi_irq_chip = {
|
|
.name = "Xilinx PCIe MSI",
|
|
.irq_enable = pci_msi_unmask_irq,
|
|
.irq_disable = pci_msi_mask_irq,
|
|
.irq_mask = pci_msi_mask_irq,
|
|
.irq_unmask = pci_msi_unmask_irq,
|
|
};
|
|
|
|
/**
|
|
* xilinx_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
|
|
* @domain: IRQ domain
|
|
* @irq: Virtual IRQ number
|
|
* @hwirq: HW interrupt number
|
|
*
|
|
* Return: Always returns 0.
|
|
*/
|
|
static int xilinx_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
|
|
irq_hw_number_t hwirq)
|
|
{
|
|
irq_set_chip_and_handler(irq, &xilinx_msi_irq_chip, handle_simple_irq);
|
|
irq_set_chip_data(irq, domain->host_data);
|
|
set_irq_flags(irq, IRQF_VALID);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* IRQ Domain operations */
|
|
static const struct irq_domain_ops msi_domain_ops = {
|
|
.map = xilinx_pcie_msi_map,
|
|
};
|
|
|
|
/**
|
|
* xilinx_pcie_enable_msi - Enable MSI support
|
|
* @port: PCIe port information
|
|
*/
|
|
static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
|
|
{
|
|
phys_addr_t msg_addr;
|
|
|
|
port->msi_pages = __get_free_pages(GFP_KERNEL, 0);
|
|
msg_addr = virt_to_phys((void *)port->msi_pages);
|
|
pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
|
|
pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
|
|
}
|
|
|
|
/* INTx Functions */
|
|
|
|
/**
|
|
* xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
|
|
* @domain: IRQ domain
|
|
* @irq: Virtual IRQ number
|
|
* @hwirq: HW interrupt number
|
|
*
|
|
* Return: Always returns 0.
|
|
*/
|
|
static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
|
|
irq_hw_number_t hwirq)
|
|
{
|
|
irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
|
|
irq_set_chip_data(irq, domain->host_data);
|
|
set_irq_flags(irq, IRQF_VALID);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* INTx IRQ Domain operations */
|
|
static const struct irq_domain_ops intx_domain_ops = {
|
|
.map = xilinx_pcie_intx_map,
|
|
};
|
|
|
|
/* PCIe HW Functions */
|
|
|
|
/**
|
|
* xilinx_pcie_intr_handler - Interrupt Service Handler
|
|
* @irq: IRQ number
|
|
* @data: PCIe port information
|
|
*
|
|
* Return: IRQ_HANDLED on success and IRQ_NONE on failure
|
|
*/
|
|
static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
|
|
{
|
|
struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
|
|
u32 val, mask, status, msi_data;
|
|
|
|
/* Read interrupt decode and mask registers */
|
|
val = pcie_read(port, XILINX_PCIE_REG_IDR);
|
|
mask = pcie_read(port, XILINX_PCIE_REG_IMR);
|
|
|
|
status = val & mask;
|
|
if (!status)
|
|
return IRQ_NONE;
|
|
|
|
if (status & XILINX_PCIE_INTR_LINK_DOWN)
|
|
dev_warn(port->dev, "Link Down\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_ECRC_ERR)
|
|
dev_warn(port->dev, "ECRC failed\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_STR_ERR)
|
|
dev_warn(port->dev, "Streaming error\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_HOT_RESET)
|
|
dev_info(port->dev, "Hot reset\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
|
|
dev_warn(port->dev, "ECAM access timeout\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_CORRECTABLE) {
|
|
dev_warn(port->dev, "Correctable error message\n");
|
|
xilinx_pcie_clear_err_interrupts(port);
|
|
}
|
|
|
|
if (status & XILINX_PCIE_INTR_NONFATAL) {
|
|
dev_warn(port->dev, "Non fatal error message\n");
|
|
xilinx_pcie_clear_err_interrupts(port);
|
|
}
|
|
|
|
if (status & XILINX_PCIE_INTR_FATAL) {
|
|
dev_warn(port->dev, "Fatal error message\n");
|
|
xilinx_pcie_clear_err_interrupts(port);
|
|
}
|
|
|
|
if (status & XILINX_PCIE_INTR_INTX) {
|
|
/* INTx interrupt received */
|
|
val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
|
|
|
|
/* Check whether interrupt valid */
|
|
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
|
|
dev_warn(port->dev, "RP Intr FIFO1 read error\n");
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/* Clear interrupt FIFO register 1 */
|
|
pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
|
|
XILINX_PCIE_REG_RPIFR1);
|
|
|
|
/* Handle INTx Interrupt */
|
|
val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
|
|
XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
|
|
generic_handle_irq(irq_find_mapping(port->irq_domain, val));
|
|
}
|
|
|
|
if (status & XILINX_PCIE_INTR_MSI) {
|
|
/* MSI Interrupt */
|
|
val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
|
|
|
|
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
|
|
dev_warn(port->dev, "RP Intr FIFO1 read error\n");
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
|
|
msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
|
|
XILINX_PCIE_RPIFR2_MSG_DATA;
|
|
|
|
/* Clear interrupt FIFO register 1 */
|
|
pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
|
|
XILINX_PCIE_REG_RPIFR1);
|
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
/* Handle MSI Interrupt */
|
|
generic_handle_irq(msi_data);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
|
|
dev_warn(port->dev, "Slave unsupported request\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_SLV_UNEXP)
|
|
dev_warn(port->dev, "Slave unexpected completion\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_SLV_COMPL)
|
|
dev_warn(port->dev, "Slave completion timeout\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_SLV_ERRP)
|
|
dev_warn(port->dev, "Slave Error Poison\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_SLV_CMPABT)
|
|
dev_warn(port->dev, "Slave Completer Abort\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
|
|
dev_warn(port->dev, "Slave Illegal Burst\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_MST_DECERR)
|
|
dev_warn(port->dev, "Master decode error\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_MST_SLVERR)
|
|
dev_warn(port->dev, "Master slave error\n");
|
|
|
|
if (status & XILINX_PCIE_INTR_MST_ERRP)
|
|
dev_warn(port->dev, "Master error poison\n");
|
|
|
|
/* Clear the Interrupt Decode register */
|
|
pcie_write(port, status, XILINX_PCIE_REG_IDR);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/**
|
|
* xilinx_pcie_free_irq_domain - Free IRQ domain
|
|
* @port: PCIe port information
|
|
*/
|
|
static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
|
|
{
|
|
int i;
|
|
u32 irq, num_irqs;
|
|
|
|
/* Free IRQ Domain */
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
|
|
free_pages(port->msi_pages, 0);
|
|
|
|
num_irqs = XILINX_NUM_MSI_IRQS;
|
|
} else {
|
|
/* INTx */
|
|
num_irqs = 4;
|
|
}
|
|
|
|
for (i = 0; i < num_irqs; i++) {
|
|
irq = irq_find_mapping(port->irq_domain, i);
|
|
if (irq > 0)
|
|
irq_dispose_mapping(irq);
|
|
}
|
|
|
|
irq_domain_remove(port->irq_domain);
|
|
}
|
|
|
|
/**
|
|
* xilinx_pcie_init_irq_domain - Initialize IRQ domain
|
|
* @port: PCIe port information
|
|
*
|
|
* Return: '0' on success and error value on failure
|
|
*/
|
|
static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
|
|
{
|
|
struct device *dev = port->dev;
|
|
struct device_node *node = dev->of_node;
|
|
struct device_node *pcie_intc_node;
|
|
|
|
/* Setup INTx */
|
|
pcie_intc_node = of_get_next_child(node, NULL);
|
|
if (!pcie_intc_node) {
|
|
dev_err(dev, "No PCIe Intc node found\n");
|
|
return PTR_ERR(pcie_intc_node);
|
|
}
|
|
|
|
port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
|
|
&intx_domain_ops,
|
|
port);
|
|
if (!port->irq_domain) {
|
|
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
|
return PTR_ERR(port->irq_domain);
|
|
}
|
|
|
|
/* Setup MSI */
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
port->irq_domain = irq_domain_add_linear(node,
|
|
XILINX_NUM_MSI_IRQS,
|
|
&msi_domain_ops,
|
|
&xilinx_pcie_msi_chip);
|
|
if (!port->irq_domain) {
|
|
dev_err(dev, "Failed to get a MSI IRQ domain\n");
|
|
return PTR_ERR(port->irq_domain);
|
|
}
|
|
|
|
xilinx_pcie_enable_msi(port);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* xilinx_pcie_init_port - Initialize hardware
|
|
* @port: PCIe port information
|
|
*/
|
|
static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
|
|
{
|
|
if (xilinx_pcie_link_is_up(port))
|
|
dev_info(port->dev, "PCIe Link is UP\n");
|
|
else
|
|
dev_info(port->dev, "PCIe Link is DOWN\n");
|
|
|
|
/* Disable all interrupts */
|
|
pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
|
|
XILINX_PCIE_REG_IMR);
|
|
|
|
/* Clear pending interrupts */
|
|
pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
|
|
XILINX_PCIE_IMR_ALL_MASK,
|
|
XILINX_PCIE_REG_IDR);
|
|
|
|
/* Enable all interrupts */
|
|
pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
|
|
|
|
/* Enable the Bridge enable bit */
|
|
pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
|
|
XILINX_PCIE_REG_RPSC_BEN,
|
|
XILINX_PCIE_REG_RPSC);
|
|
}
|
|
|
|
/**
|
|
* xilinx_pcie_setup - Setup memory resources
|
|
* @nr: Bus number
|
|
* @sys: Per controller structure
|
|
*
|
|
* Return: '1' on success and error value on failure
|
|
*/
|
|
static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys)
|
|
{
|
|
struct xilinx_pcie_port *port = sys_to_pcie(sys);
|
|
|
|
list_splice_init(&port->resources, &sys->resources);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* xilinx_pcie_scan_bus - Scan PCIe bus for devices
|
|
* @nr: Bus number
|
|
* @sys: Per controller structure
|
|
*
|
|
* Return: Valid Bus pointer on success and NULL on failure
|
|
*/
|
|
static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
|
|
{
|
|
struct xilinx_pcie_port *port = sys_to_pcie(sys);
|
|
struct pci_bus *bus;
|
|
|
|
port->root_busno = sys->busnr;
|
|
bus = pci_scan_root_bus(port->dev, sys->busnr, &xilinx_pcie_ops,
|
|
sys, &sys->resources);
|
|
|
|
return bus;
|
|
}
|
|
|
|
/**
|
|
* xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
|
|
* @port: PCIe port information
|
|
*
|
|
* Return: '0' on success and error value on failure
|
|
*/
|
|
static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
|
|
{
|
|
struct device *dev = port->dev;
|
|
struct device_node *node = dev->of_node;
|
|
struct resource *mem;
|
|
resource_size_t offset;
|
|
struct of_pci_range_parser parser;
|
|
struct of_pci_range range;
|
|
struct resource_entry *win;
|
|
int err = 0, mem_resno = 0;
|
|
|
|
/* Get the ranges */
|
|
if (of_pci_range_parser_init(&parser, node)) {
|
|
dev_err(dev, "missing \"ranges\" property\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Parse the ranges and add the resources found to the list */
|
|
for_each_of_pci_range(&parser, &range) {
|
|
|
|
if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
|
|
dev_err(dev, "Maximum memory resources exceeded\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
|
|
if (!mem) {
|
|
err = -ENOMEM;
|
|
goto free_resources;
|
|
}
|
|
|
|
of_pci_range_to_resource(&range, node, mem);
|
|
|
|
switch (mem->flags & IORESOURCE_TYPE_BITS) {
|
|
case IORESOURCE_MEM:
|
|
offset = range.cpu_addr - range.pci_addr;
|
|
mem_resno++;
|
|
break;
|
|
default:
|
|
err = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
if (err < 0) {
|
|
dev_warn(dev, "Invalid resource found %pR\n", mem);
|
|
continue;
|
|
}
|
|
|
|
err = request_resource(&iomem_resource, mem);
|
|
if (err)
|
|
goto free_resources;
|
|
|
|
pci_add_resource_offset(&port->resources, mem, offset);
|
|
}
|
|
|
|
/* Get the bus range */
|
|
if (of_pci_parse_bus_range(node, &port->bus_range)) {
|
|
u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
|
|
u8 last;
|
|
|
|
last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
|
|
XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
|
|
|
|
port->bus_range = (struct resource) {
|
|
.name = node->name,
|
|
.start = 0,
|
|
.end = last,
|
|
.flags = IORESOURCE_BUS,
|
|
};
|
|
}
|
|
|
|
/* Register bus resource */
|
|
pci_add_resource(&port->resources, &port->bus_range);
|
|
|
|
return 0;
|
|
|
|
free_resources:
|
|
release_child_resources(&iomem_resource);
|
|
resource_list_for_each_entry(win, &port->resources)
|
|
devm_kfree(dev, win->res);
|
|
pci_free_resource_list(&port->resources);
|
|
|
|
return err;
|
|
}
|
|
|
|
/**
|
|
* xilinx_pcie_parse_dt - Parse Device tree
|
|
* @port: PCIe port information
|
|
*
|
|
* Return: '0' on success and error value on failure
|
|
*/
|
|
static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
|
|
{
|
|
struct device *dev = port->dev;
|
|
struct device_node *node = dev->of_node;
|
|
struct resource regs;
|
|
const char *type;
|
|
int err;
|
|
|
|
type = of_get_property(node, "device_type", NULL);
|
|
if (!type || strcmp(type, "pci")) {
|
|
dev_err(dev, "invalid \"device_type\" %s\n", type);
|
|
return -EINVAL;
|
|
}
|
|
|
|
err = of_address_to_resource(node, 0, ®s);
|
|
if (err) {
|
|
dev_err(dev, "missing \"reg\" property\n");
|
|
return err;
|
|
}
|
|
|
|
port->reg_base = devm_ioremap_resource(dev, ®s);
|
|
if (IS_ERR(port->reg_base))
|
|
return PTR_ERR(port->reg_base);
|
|
|
|
port->irq = irq_of_parse_and_map(node, 0);
|
|
err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
|
|
IRQF_SHARED, "xilinx-pcie", port);
|
|
if (err) {
|
|
dev_err(dev, "unable to request irq %d\n", port->irq);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* xilinx_pcie_probe - Probe function
|
|
* @pdev: Platform device pointer
|
|
*
|
|
* Return: '0' on success and error value on failure
|
|
*/
|
|
static int xilinx_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct xilinx_pcie_port *port;
|
|
struct hw_pci hw;
|
|
struct device *dev = &pdev->dev;
|
|
int err;
|
|
|
|
if (!dev->of_node)
|
|
return -ENODEV;
|
|
|
|
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
|
|
if (!port)
|
|
return -ENOMEM;
|
|
|
|
port->dev = dev;
|
|
|
|
err = xilinx_pcie_parse_dt(port);
|
|
if (err) {
|
|
dev_err(dev, "Parsing DT failed\n");
|
|
return err;
|
|
}
|
|
|
|
xilinx_pcie_init_port(port);
|
|
|
|
err = xilinx_pcie_init_irq_domain(port);
|
|
if (err) {
|
|
dev_err(dev, "Failed creating IRQ Domain\n");
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* Parse PCI ranges, configuration bus range and
|
|
* request their resources
|
|
*/
|
|
INIT_LIST_HEAD(&port->resources);
|
|
err = xilinx_pcie_parse_and_add_res(port);
|
|
if (err) {
|
|
dev_err(dev, "Failed adding resources\n");
|
|
return err;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, port);
|
|
|
|
/* Register the device */
|
|
memset(&hw, 0, sizeof(hw));
|
|
hw = (struct hw_pci) {
|
|
.nr_controllers = 1,
|
|
.private_data = (void **)&port,
|
|
.setup = xilinx_pcie_setup,
|
|
.map_irq = of_irq_parse_and_map_pci,
|
|
.scan = xilinx_pcie_scan_bus,
|
|
.ops = &xilinx_pcie_ops,
|
|
};
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
xilinx_pcie_msi_chip.dev = port->dev;
|
|
hw.msi_ctrl = &xilinx_pcie_msi_chip;
|
|
#endif
|
|
pci_common_init_dev(dev, &hw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* xilinx_pcie_remove - Remove function
|
|
* @pdev: Platform device pointer
|
|
*
|
|
* Return: '0' always
|
|
*/
|
|
static int xilinx_pcie_remove(struct platform_device *pdev)
|
|
{
|
|
struct xilinx_pcie_port *port = platform_get_drvdata(pdev);
|
|
|
|
xilinx_pcie_free_irq_domain(port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id xilinx_pcie_of_match[] = {
|
|
{ .compatible = "xlnx,axi-pcie-host-1.00.a", },
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver xilinx_pcie_driver = {
|
|
.driver = {
|
|
.name = "xilinx-pcie",
|
|
.of_match_table = xilinx_pcie_of_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = xilinx_pcie_probe,
|
|
.remove = xilinx_pcie_remove,
|
|
};
|
|
module_platform_driver(xilinx_pcie_driver);
|
|
|
|
MODULE_AUTHOR("Xilinx Inc");
|
|
MODULE_DESCRIPTION("Xilinx AXI PCIe driver");
|
|
MODULE_LICENSE("GPL v2");
|