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![Chris Wilson](/assets/img/avatar_default.png)
The assertion that we want to make before disabling the pin of the pages for the unknown swizzling quirk is that the quirk is indeed active, and that the quirk is disabled before we do apply it to the pages. Fixes:2c3a3f44dc
("drm/i915: Fix pages pin counting around swizzle quirk") Fixes:957870f934
("drm/i915: Split out i915_gem_object_set_tiling()") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170521124014.27678-1-chris@chris-wilson.co.uk Reviewed-bhy: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
455 lines
13 KiB
C
455 lines
13 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include <linux/string.h>
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#include <linux/bitops.h>
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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/**
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* DOC: buffer object tiling
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*
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* i915_gem_set_tiling_ioctl() and i915_gem_get_tiling_ioctl() is the userspace
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* interface to declare fence register requirements.
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*
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* In principle GEM doesn't care at all about the internal data layout of an
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* object, and hence it also doesn't care about tiling or swizzling. There's two
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* exceptions:
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*
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* - For X and Y tiling the hardware provides detilers for CPU access, so called
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* fences. Since there's only a limited amount of them the kernel must manage
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* these, and therefore userspace must tell the kernel the object tiling if it
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* wants to use fences for detiling.
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* - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
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* depends upon the physical page frame number. When swapping such objects the
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* page frame number might change and the kernel must be able to fix this up
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* and hence now the tiling. Note that on a subset of platforms with
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* asymmetric memory channel population the swizzling pattern changes in an
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* unknown way, and for those the kernel simply forbids swapping completely.
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*
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* Since neither of this applies for new tiling layouts on modern platforms like
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* W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
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* Anything else can be handled in userspace entirely without the kernel's
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* invovlement.
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*/
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/**
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* i915_gem_fence_size - required global GTT size for a fence
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* @i915: i915 device
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* @size: object size
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* @tiling: tiling mode
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* @stride: tiling stride
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*
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* Return the required global GTT size for a fence (view of a tiled object),
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* taking into account potential fence register mapping.
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*/
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u32 i915_gem_fence_size(struct drm_i915_private *i915,
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u32 size, unsigned int tiling, unsigned int stride)
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{
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u32 ggtt_size;
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GEM_BUG_ON(!size);
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if (tiling == I915_TILING_NONE)
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return size;
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GEM_BUG_ON(!stride);
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if (INTEL_GEN(i915) >= 4) {
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stride *= i915_gem_tile_height(tiling);
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GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
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return roundup(size, stride);
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}
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/* Previous chips need a power-of-two fence region when tiling */
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if (IS_GEN3(i915))
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ggtt_size = 1024*1024;
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else
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ggtt_size = 512*1024;
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while (ggtt_size < size)
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ggtt_size <<= 1;
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return ggtt_size;
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}
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/**
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* i915_gem_fence_alignment - required global GTT alignment for a fence
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* @i915: i915 device
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* @size: object size
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* @tiling: tiling mode
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* @stride: tiling stride
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*
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* Return the required global GTT alignment for a fence (a view of a tiled
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* object), taking into account potential fence register mapping.
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*/
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u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
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unsigned int tiling, unsigned int stride)
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{
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GEM_BUG_ON(!size);
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/*
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* Minimum alignment is 4k (GTT page size), but might be greater
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* if a fence register is needed for the object.
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*/
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if (tiling == I915_TILING_NONE)
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return I915_GTT_MIN_ALIGNMENT;
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if (INTEL_GEN(i915) >= 4)
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return I965_FENCE_PAGE;
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/*
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* Previous chips need to be aligned to the size of the smallest
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* fence register that can contain the object.
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*/
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return i915_gem_fence_size(i915, size, tiling, stride);
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}
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/* Check pitch constriants for all chips & tiling formats */
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static bool
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i915_tiling_ok(struct drm_i915_gem_object *obj,
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unsigned int tiling, unsigned int stride)
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{
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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unsigned int tile_width;
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/* Linear is always fine */
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if (tiling == I915_TILING_NONE)
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return true;
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if (tiling > I915_TILING_LAST)
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return false;
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/* check maximum stride & object size */
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/* i965+ stores the end address of the gtt mapping in the fence
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* reg, so dont bother to check the size */
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if (INTEL_GEN(i915) >= 7) {
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if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
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return false;
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} else if (INTEL_GEN(i915) >= 4) {
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if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
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return false;
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} else {
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if (stride > 8192)
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return false;
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if (!is_power_of_2(stride))
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return false;
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}
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if (IS_GEN2(i915) ||
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(tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
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tile_width = 128;
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else
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tile_width = 512;
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if (!stride || !IS_ALIGNED(stride, tile_width))
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return false;
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return true;
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}
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static bool i915_vma_fence_prepare(struct i915_vma *vma,
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int tiling_mode, unsigned int stride)
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{
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struct drm_i915_private *i915 = vma->vm->i915;
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u32 size, alignment;
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if (!i915_vma_is_map_and_fenceable(vma))
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return true;
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size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
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if (vma->node.size < size)
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return false;
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alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
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if (!IS_ALIGNED(vma->node.start, alignment))
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return false;
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return true;
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}
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/* Make the current GTT allocation valid for the change in tiling. */
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static int
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i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
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int tiling_mode, unsigned int stride)
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{
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struct i915_vma *vma;
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int ret;
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if (tiling_mode == I915_TILING_NONE)
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return 0;
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list_for_each_entry(vma, &obj->vma_list, obj_link) {
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if (!i915_vma_is_ggtt(vma))
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break;
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if (i915_vma_fence_prepare(vma, tiling_mode, stride))
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continue;
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ret = i915_vma_unbind(vma);
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if (ret)
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return ret;
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}
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return 0;
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}
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int
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i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
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unsigned int tiling, unsigned int stride)
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{
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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struct i915_vma *vma;
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int err;
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/* Make sure we don't cross-contaminate obj->tiling_and_stride */
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BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
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GEM_BUG_ON(!i915_tiling_ok(obj, tiling, stride));
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GEM_BUG_ON(!stride ^ (tiling == I915_TILING_NONE));
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lockdep_assert_held(&i915->drm.struct_mutex);
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if ((tiling | stride) == obj->tiling_and_stride)
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return 0;
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if (i915_gem_object_is_framebuffer(obj))
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return -EBUSY;
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/* We need to rebind the object if its current allocation
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* no longer meets the alignment restrictions for its new
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* tiling mode. Otherwise we can just leave it alone, but
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* need to ensure that any fence register is updated before
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* the next fenced (either through the GTT or by the BLT unit
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* on older GPUs) access.
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*
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* After updating the tiling parameters, we then flag whether
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* we need to update an associated fence register. Note this
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* has to also include the unfenced register the GPU uses
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* whilst executing a fenced command for an untiled object.
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*/
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err = i915_gem_object_fence_prepare(obj, tiling, stride);
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if (err)
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return err;
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i915_gem_object_lock(obj);
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if (i915_gem_object_is_framebuffer(obj)) {
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i915_gem_object_unlock(obj);
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return -EBUSY;
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}
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/* If the memory has unknown (i.e. varying) swizzling, we pin the
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* pages to prevent them being swapped out and causing corruption
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* due to the change in swizzling.
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*/
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mutex_lock(&obj->mm.lock);
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if (obj->mm.pages &&
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obj->mm.madv == I915_MADV_WILLNEED &&
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i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
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if (tiling == I915_TILING_NONE) {
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GEM_BUG_ON(!obj->mm.quirked);
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__i915_gem_object_unpin_pages(obj);
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obj->mm.quirked = false;
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}
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if (!i915_gem_object_is_tiled(obj)) {
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GEM_BUG_ON(obj->mm.quirked);
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__i915_gem_object_pin_pages(obj);
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obj->mm.quirked = true;
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}
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}
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mutex_unlock(&obj->mm.lock);
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list_for_each_entry(vma, &obj->vma_list, obj_link) {
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if (!i915_vma_is_ggtt(vma))
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break;
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vma->fence_size =
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i915_gem_fence_size(i915, vma->size, tiling, stride);
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vma->fence_alignment =
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i915_gem_fence_alignment(i915,
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vma->size, tiling, stride);
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if (vma->fence)
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vma->fence->dirty = true;
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}
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obj->tiling_and_stride = tiling | stride;
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i915_gem_object_unlock(obj);
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/* Force the fence to be reacquired for GTT access */
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i915_gem_release_mmap(obj);
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/* Try to preallocate memory required to save swizzling on put-pages */
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if (i915_gem_object_needs_bit17_swizzle(obj)) {
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if (!obj->bit_17) {
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obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
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sizeof(long), GFP_KERNEL);
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}
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} else {
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kfree(obj->bit_17);
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obj->bit_17 = NULL;
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}
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return 0;
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}
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/**
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* i915_gem_set_tiling_ioctl - IOCTL handler to set tiling mode
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* @dev: DRM device
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* @data: data pointer for the ioctl
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* @file: DRM file for the ioctl call
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*
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* Sets the tiling mode of an object, returning the required swizzling of
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* bit 6 of addresses in the object.
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*
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* Called by the user via ioctl.
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*
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* Returns:
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* Zero on success, negative errno on failure.
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*/
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int
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i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_i915_gem_set_tiling *args = data;
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struct drm_i915_gem_object *obj;
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int err;
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obj = i915_gem_object_lookup(file, args->handle);
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if (!obj)
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return -ENOENT;
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if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {
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err = -EINVAL;
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goto err;
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}
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if (args->tiling_mode == I915_TILING_NONE) {
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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args->stride = 0;
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} else {
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if (args->tiling_mode == I915_TILING_X)
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args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_x;
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else
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args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_y;
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/* Hide bit 17 swizzling from the user. This prevents old Mesa
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* from aborting the application on sw fallbacks to bit 17,
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* and we use the pread/pwrite bit17 paths to swizzle for it.
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* If there was a user that was relying on the swizzle
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* information for drm_intel_bo_map()ed reads/writes this would
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* break it, but we don't have any of those.
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*/
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
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args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
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args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
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/* If we can't handle the swizzling, make it untiled. */
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
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args->tiling_mode = I915_TILING_NONE;
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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args->stride = 0;
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}
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}
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err = mutex_lock_interruptible(&dev->struct_mutex);
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if (err)
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goto err;
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err = i915_gem_object_set_tiling(obj, args->tiling_mode, args->stride);
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mutex_unlock(&dev->struct_mutex);
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/* We have to maintain this existing ABI... */
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args->stride = i915_gem_object_get_stride(obj);
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args->tiling_mode = i915_gem_object_get_tiling(obj);
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err:
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i915_gem_object_put(obj);
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return err;
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}
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/**
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* i915_gem_get_tiling_ioctl - IOCTL handler to get tiling mode
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* @dev: DRM device
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* @data: data pointer for the ioctl
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* @file: DRM file for the ioctl call
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*
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* Returns the current tiling mode and required bit 6 swizzling for the object.
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*
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* Called by the user via ioctl.
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*
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* Returns:
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* Zero on success, negative errno on failure.
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*/
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int
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i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_i915_gem_get_tiling *args = data;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_gem_object *obj;
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int err = -ENOENT;
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rcu_read_lock();
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obj = i915_gem_object_lookup_rcu(file, args->handle);
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if (obj) {
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args->tiling_mode =
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READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
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err = 0;
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}
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rcu_read_unlock();
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if (unlikely(err))
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return err;
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switch (args->tiling_mode) {
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case I915_TILING_X:
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
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break;
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case I915_TILING_Y:
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
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break;
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default:
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case I915_TILING_NONE:
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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break;
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}
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/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
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if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
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args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
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else
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args->phys_swizzle_mode = args->swizzle_mode;
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
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args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
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args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
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return 0;
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}
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