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![Rodrigo Vivi](/assets/img/avatar_default.png)
Although CNL follows PLL initialization more like Skylake than Broxton we have a completely different initialization sequence and registers used. One big difference from SKL is that CDCLK PLL is now exclusive (ADPLL) and for DDIs and MIPI we need to use DFGPLLs 0, 1 or 2. v2: Accept all Ander's suggestions and fixes: - Registers and bits names prefix - Group pll functions - bits masks fixes - remove read and modify on cfgcr1 - fix cfgcr0 setup v3: Set SSC_ENABLE for DP. Fix HDMI_MODE cfgcr0. Avoid touch cfgcr0 on DP. Add missed else on dpll_mgr definition so we use cnl one, not hsw. v3: Centra freq should be always set to default and change bits definitions to (1 << 1) instead of (1<<1). (by Paulo) v4: Rebased. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Kahola, Mika <mika.kahola@intel.com> Reviewed-by: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-7-git-send-email-rodrigo.vivi@intel.com
289 lines
7.4 KiB
C
289 lines
7.4 KiB
C
/*
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* Copyright © 2012-2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_DPLL_MGR_H_
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#define _INTEL_DPLL_MGR_H_
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/*FIXME: Move this to a more appropriate place. */
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#define abs_diff(a, b) ({ \
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typeof(a) __a = (a); \
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typeof(b) __b = (b); \
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(void) (&__a == &__b); \
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__a > __b ? (__a - __b) : (__b - __a); })
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struct drm_i915_private;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_encoder;
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struct intel_shared_dpll;
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struct intel_dpll_mgr;
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/**
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* enum intel_dpll_id - possible DPLL ids
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*
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* Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
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*/
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enum intel_dpll_id {
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/**
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* @DPLL_ID_PRIVATE: non-shared dpll in use
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*/
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DPLL_ID_PRIVATE = -1,
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/**
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* @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
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*/
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DPLL_ID_PCH_PLL_A = 0,
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/**
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* @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
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*/
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DPLL_ID_PCH_PLL_B = 1,
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/**
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* @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
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*/
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DPLL_ID_WRPLL1 = 0,
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/**
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* @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
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*/
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DPLL_ID_WRPLL2 = 1,
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/**
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* @DPLL_ID_SPLL: HSW and BDW SPLL
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*/
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DPLL_ID_SPLL = 2,
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/**
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* @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
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*/
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DPLL_ID_LCPLL_810 = 3,
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/**
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* @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
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*/
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DPLL_ID_LCPLL_1350 = 4,
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/**
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* @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
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*/
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DPLL_ID_LCPLL_2700 = 5,
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/**
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* @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
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*/
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DPLL_ID_SKL_DPLL0 = 0,
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/**
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* @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
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*/
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DPLL_ID_SKL_DPLL1 = 1,
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/**
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* @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
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*/
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DPLL_ID_SKL_DPLL2 = 2,
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/**
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* @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
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*/
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DPLL_ID_SKL_DPLL3 = 3,
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};
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#define I915_NUM_PLLS 6
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struct intel_dpll_hw_state {
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/* i9xx, pch plls */
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uint32_t dpll;
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uint32_t dpll_md;
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uint32_t fp0;
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uint32_t fp1;
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/* hsw, bdw */
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uint32_t wrpll;
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uint32_t spll;
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/* skl */
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/*
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* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
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* lower part of ctrl1 and they get shifted into position when writing
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* the register. This allows us to easily compare the state to share
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* the DPLL.
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*/
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uint32_t ctrl1;
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/* HDMI only, 0 when used for DP */
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uint32_t cfgcr1, cfgcr2;
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/* cnl */
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uint32_t cfgcr0;
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/* CNL also uses cfgcr1 */
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/* bxt */
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uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
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pcsdw12;
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};
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/**
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* struct intel_shared_dpll_state - hold the DPLL atomic state
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*
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* This structure holds an atomic state for the DPLL, that can represent
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* either its current state (in struct &intel_shared_dpll) or a desired
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* future state which would be applied by an atomic mode set (stored in
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* a struct &intel_atomic_state).
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*
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* See also intel_get_shared_dpll() and intel_release_shared_dpll().
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*/
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struct intel_shared_dpll_state {
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/**
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* @crtc_mask: mask of CRTC using this DPLL, active or not
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*/
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unsigned crtc_mask;
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/**
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* @hw_state: hardware configuration for the DPLL stored in
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* struct &intel_dpll_hw_state.
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*/
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struct intel_dpll_hw_state hw_state;
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};
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/**
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* struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
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*/
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struct intel_shared_dpll_funcs {
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/**
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* @prepare:
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*
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* Optional hook to perform operations prior to enabling the PLL.
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* Called from intel_prepare_shared_dpll() function unless the PLL
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* is already enabled.
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*/
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void (*prepare)(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll);
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/**
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* @enable:
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*
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* Hook for enabling the pll, called from intel_enable_shared_dpll()
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* if the pll is not already enabled.
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*/
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void (*enable)(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll);
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/**
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* @disable:
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*
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* Hook for disabling the pll, called from intel_disable_shared_dpll()
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* only when it is safe to disable the pll, i.e., there are no more
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* tracked users for it.
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*/
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void (*disable)(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll);
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/**
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* @get_hw_state:
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*
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* Hook for reading the values currently programmed to the DPLL
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* registers. This is used for initial hw state readout and state
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* verification after a mode set.
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*/
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bool (*get_hw_state)(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll,
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struct intel_dpll_hw_state *hw_state);
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};
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/**
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* struct intel_shared_dpll - display PLL with tracked state and users
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*/
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struct intel_shared_dpll {
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/**
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* @state:
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*
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* Store the state for the pll, including the its hw state
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* and CRTCs using it.
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*/
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struct intel_shared_dpll_state state;
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/**
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* @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL
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*/
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unsigned active_mask;
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/**
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* @on: is the PLL actually active? Disabled during modeset
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*/
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bool on;
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/**
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* @name: DPLL name; used for logging
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*/
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const char *name;
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/**
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* @id: unique indentifier for this DPLL; should match the index in the
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* dev_priv->shared_dplls array
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*/
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enum intel_dpll_id id;
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/**
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* @funcs: platform specific hooks
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*/
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struct intel_shared_dpll_funcs funcs;
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#define INTEL_DPLL_ALWAYS_ON (1 << 0)
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/**
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* @flags:
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*
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* INTEL_DPLL_ALWAYS_ON
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* Inform the state checker that the DPLL is kept enabled even if
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* not in use by any CRTC.
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*/
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uint32_t flags;
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};
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#define SKL_DPLL0 0
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#define SKL_DPLL1 1
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#define SKL_DPLL2 2
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#define SKL_DPLL3 3
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/* shared dpll functions */
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struct intel_shared_dpll *
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intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
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enum intel_dpll_id id);
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enum intel_dpll_id
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intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll);
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void assert_shared_dpll(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll,
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bool state);
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#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
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#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
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struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
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struct intel_crtc_state *state,
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struct intel_encoder *encoder);
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void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
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struct intel_crtc *crtc,
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struct drm_atomic_state *state);
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void intel_prepare_shared_dpll(struct intel_crtc *crtc);
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void intel_enable_shared_dpll(struct intel_crtc *crtc);
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void intel_disable_shared_dpll(struct intel_crtc *crtc);
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void intel_shared_dpll_swap_state(struct drm_atomic_state *state);
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void intel_shared_dpll_init(struct drm_device *dev);
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void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
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struct intel_dpll_hw_state *hw_state);
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#endif /* _INTEL_DPLL_MGR_H_ */
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