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![Mika Kuoppala](/assets/img/avatar_default.png)
As we emulate execlists on top of the GuC workqueue, it is not restricted to just 2 ports and we can increase that number arbitrarily to trade-off queue depth (i.e. scheduling latency) against pipeline bubbles. v2: rebase. better commit msg (Chris) v3: rebase Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170922124307.10914-5-mika.kuoppala@intel.com
1583 lines
43 KiB
C
1583 lines
43 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "i915_drv.h"
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#include "intel_ringbuffer.h"
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#include "intel_lrc.h"
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/* Haswell does have the CXT_SIZE register however it does not appear to be
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* valid. Now, docs explain in dwords what is in the context object. The full
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* size is 70720 bytes, however, the power context and execlist context will
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* never be saved (power context is stored elsewhere, and execlists don't work
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* on HSW) - so the final size, including the extra state required for the
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* Resource Streamer, is 66944 bytes, which rounds to 17 pages.
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*/
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#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
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/* Same as Haswell, but 72064 bytes now. */
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#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
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#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
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#define GEN10_LR_CONTEXT_RENDER_SIZE (19 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
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struct engine_class_info {
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const char *name;
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int (*init_legacy)(struct intel_engine_cs *engine);
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int (*init_execlists)(struct intel_engine_cs *engine);
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};
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static const struct engine_class_info intel_engine_classes[] = {
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[RENDER_CLASS] = {
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.name = "rcs",
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.init_execlists = logical_render_ring_init,
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.init_legacy = intel_init_render_ring_buffer,
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},
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[COPY_ENGINE_CLASS] = {
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.name = "bcs",
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.init_execlists = logical_xcs_ring_init,
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.init_legacy = intel_init_blt_ring_buffer,
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},
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[VIDEO_DECODE_CLASS] = {
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.name = "vcs",
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.init_execlists = logical_xcs_ring_init,
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.init_legacy = intel_init_bsd_ring_buffer,
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},
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[VIDEO_ENHANCEMENT_CLASS] = {
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.name = "vecs",
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.init_execlists = logical_xcs_ring_init,
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.init_legacy = intel_init_vebox_ring_buffer,
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},
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};
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struct engine_info {
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unsigned int hw_id;
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unsigned int uabi_id;
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u8 class;
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u8 instance;
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u32 mmio_base;
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unsigned irq_shift;
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};
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static const struct engine_info intel_engines[] = {
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[RCS] = {
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.hw_id = RCS_HW,
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.uabi_id = I915_EXEC_RENDER,
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.class = RENDER_CLASS,
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.instance = 0,
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.mmio_base = RENDER_RING_BASE,
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.irq_shift = GEN8_RCS_IRQ_SHIFT,
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},
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[BCS] = {
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.hw_id = BCS_HW,
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.uabi_id = I915_EXEC_BLT,
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.class = COPY_ENGINE_CLASS,
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.instance = 0,
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.mmio_base = BLT_RING_BASE,
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.irq_shift = GEN8_BCS_IRQ_SHIFT,
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},
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[VCS] = {
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.hw_id = VCS_HW,
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.uabi_id = I915_EXEC_BSD,
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.class = VIDEO_DECODE_CLASS,
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.instance = 0,
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.mmio_base = GEN6_BSD_RING_BASE,
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.irq_shift = GEN8_VCS1_IRQ_SHIFT,
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},
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[VCS2] = {
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.hw_id = VCS2_HW,
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.uabi_id = I915_EXEC_BSD,
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.class = VIDEO_DECODE_CLASS,
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.instance = 1,
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.mmio_base = GEN8_BSD2_RING_BASE,
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.irq_shift = GEN8_VCS2_IRQ_SHIFT,
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},
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[VECS] = {
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.hw_id = VECS_HW,
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.uabi_id = I915_EXEC_VEBOX,
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.class = VIDEO_ENHANCEMENT_CLASS,
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.instance = 0,
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.mmio_base = VEBOX_RING_BASE,
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.irq_shift = GEN8_VECS_IRQ_SHIFT,
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},
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};
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/**
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* ___intel_engine_context_size() - return the size of the context for an engine
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* @dev_priv: i915 device private
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* @class: engine class
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*
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* Each engine class may require a different amount of space for a context
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* image.
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*
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* Return: size (in bytes) of an engine class specific context image
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*
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* Note: this size includes the HWSP, which is part of the context image
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* in LRC mode, but does not include the "shared data page" used with
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* GuC submission. The caller should account for this if using the GuC.
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*/
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static u32
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__intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
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{
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u32 cxt_size;
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BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
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switch (class) {
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case RENDER_CLASS:
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switch (INTEL_GEN(dev_priv)) {
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default:
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MISSING_CASE(INTEL_GEN(dev_priv));
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case 10:
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return GEN10_LR_CONTEXT_RENDER_SIZE;
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case 9:
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return GEN9_LR_CONTEXT_RENDER_SIZE;
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case 8:
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return i915_modparams.enable_execlists ?
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GEN8_LR_CONTEXT_RENDER_SIZE :
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GEN8_CXT_TOTAL_SIZE;
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case 7:
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if (IS_HASWELL(dev_priv))
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return HSW_CXT_TOTAL_SIZE;
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cxt_size = I915_READ(GEN7_CXT_SIZE);
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return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
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PAGE_SIZE);
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case 6:
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cxt_size = I915_READ(CXT_SIZE);
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return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
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PAGE_SIZE);
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case 5:
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case 4:
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case 3:
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case 2:
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/* For the special day when i810 gets merged. */
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case 1:
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return 0;
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}
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break;
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default:
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MISSING_CASE(class);
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case VIDEO_DECODE_CLASS:
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case VIDEO_ENHANCEMENT_CLASS:
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case COPY_ENGINE_CLASS:
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if (INTEL_GEN(dev_priv) < 8)
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return 0;
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return GEN8_LR_CONTEXT_OTHER_SIZE;
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}
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}
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static int
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intel_engine_setup(struct drm_i915_private *dev_priv,
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enum intel_engine_id id)
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{
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const struct engine_info *info = &intel_engines[id];
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const struct engine_class_info *class_info;
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struct intel_engine_cs *engine;
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GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes));
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class_info = &intel_engine_classes[info->class];
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GEM_BUG_ON(dev_priv->engine[id]);
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engine = kzalloc(sizeof(*engine), GFP_KERNEL);
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if (!engine)
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return -ENOMEM;
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engine->id = id;
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engine->i915 = dev_priv;
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WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s%u",
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class_info->name, info->instance) >=
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sizeof(engine->name));
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engine->uabi_id = info->uabi_id;
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engine->hw_id = engine->guc_id = info->hw_id;
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engine->mmio_base = info->mmio_base;
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engine->irq_shift = info->irq_shift;
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engine->class = info->class;
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engine->instance = info->instance;
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engine->context_size = __intel_engine_context_size(dev_priv,
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engine->class);
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if (WARN_ON(engine->context_size > BIT(20)))
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engine->context_size = 0;
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/* Nothing to do here, execute in order of dependencies */
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engine->schedule = NULL;
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ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
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dev_priv->engine[id] = engine;
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return 0;
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}
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/**
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* intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
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* @dev_priv: i915 device private
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*
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* Return: non-zero if the initialization failed.
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*/
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int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
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{
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struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
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const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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unsigned int mask = 0;
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unsigned int i;
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int err;
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WARN_ON(ring_mask == 0);
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WARN_ON(ring_mask &
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GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
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for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
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if (!HAS_ENGINE(dev_priv, i))
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continue;
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err = intel_engine_setup(dev_priv, i);
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if (err)
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goto cleanup;
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mask |= ENGINE_MASK(i);
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}
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/*
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* Catch failures to update intel_engines table when the new engines
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* are added to the driver by a warning and disabling the forgotten
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* engines.
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*/
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if (WARN_ON(mask != ring_mask))
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device_info->ring_mask = mask;
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/* We always presume we have at least RCS available for later probing */
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if (WARN_ON(!HAS_ENGINE(dev_priv, RCS))) {
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err = -ENODEV;
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goto cleanup;
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}
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device_info->num_rings = hweight32(mask);
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return 0;
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cleanup:
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for_each_engine(engine, dev_priv, id)
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kfree(engine);
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return err;
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}
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/**
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* intel_engines_init() - init the Engine Command Streamers
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* @dev_priv: i915 device private
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*
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* Return: non-zero if the initialization failed.
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*/
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int intel_engines_init(struct drm_i915_private *dev_priv)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id, err_id;
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int err;
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for_each_engine(engine, dev_priv, id) {
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const struct engine_class_info *class_info =
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&intel_engine_classes[engine->class];
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int (*init)(struct intel_engine_cs *engine);
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if (i915_modparams.enable_execlists)
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init = class_info->init_execlists;
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else
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init = class_info->init_legacy;
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err = -EINVAL;
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err_id = id;
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if (GEM_WARN_ON(!init))
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goto cleanup;
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err = init(engine);
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if (err)
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goto cleanup;
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GEM_BUG_ON(!engine->submit_request);
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}
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return 0;
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cleanup:
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for_each_engine(engine, dev_priv, id) {
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if (id >= err_id) {
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kfree(engine);
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dev_priv->engine[id] = NULL;
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} else {
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dev_priv->gt.cleanup_engine(engine);
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}
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}
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return err;
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}
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void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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/* Our semaphore implementation is strictly monotonic (i.e. we proceed
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* so long as the semaphore value in the register/page is greater
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* than the sync value), so whenever we reset the seqno,
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* so long as we reset the tracking semaphore value to 0, it will
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* always be before the next request's seqno. If we don't reset
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* the semaphore value, then when the seqno moves backwards all
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* future waits will complete instantly (causing rendering corruption).
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*/
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if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
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I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
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I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
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if (HAS_VEBOX(dev_priv))
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I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
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}
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if (dev_priv->semaphore) {
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struct page *page = i915_vma_first_page(dev_priv->semaphore);
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void *semaphores;
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/* Semaphores are in noncoherent memory, flush to be safe */
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semaphores = kmap_atomic(page);
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memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
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0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
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drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
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I915_NUM_ENGINES * gen8_semaphore_seqno_size);
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kunmap_atomic(semaphores);
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}
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intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
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clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
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/* After manually advancing the seqno, fake the interrupt in case
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* there are any waiters for that seqno.
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*/
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intel_engine_wakeup(engine);
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GEM_BUG_ON(intel_engine_get_seqno(engine) != seqno);
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}
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static void intel_engine_init_timeline(struct intel_engine_cs *engine)
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{
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engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
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}
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static bool csb_force_mmio(struct drm_i915_private *i915)
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{
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/* GVT emulation depends upon intercepting CSB mmio */
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if (intel_vgpu_active(i915))
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return true;
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/*
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* IOMMU adds unpredictable latency causing the CSB write (from the
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* GPU into the HWSP) to only be visible some time after the interrupt
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* (missed breadcrumb syndrome).
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*/
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if (intel_vtd_active())
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return true;
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return false;
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}
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|
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static void intel_engine_init_execlist(struct intel_engine_cs *engine)
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{
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struct intel_engine_execlists * const execlists = &engine->execlists;
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execlists->csb_use_mmio = csb_force_mmio(engine->i915);
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execlists->port_mask = 1;
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BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists));
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GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
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execlists->queue = RB_ROOT;
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execlists->first = NULL;
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}
|
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|
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/**
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* intel_engines_setup_common - setup engine state not requiring hw access
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* @engine: Engine to setup.
|
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*
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* Initializes @engine@ structure members shared between legacy and execlists
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* submission modes which do not require hardware access.
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*
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* Typically done early in the submission mode specific engine setup stage.
|
|
*/
|
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void intel_engine_setup_common(struct intel_engine_cs *engine)
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{
|
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intel_engine_init_execlist(engine);
|
|
|
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intel_engine_init_timeline(engine);
|
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intel_engine_init_hangcheck(engine);
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i915_gem_batch_pool_init(engine, &engine->batch_pool);
|
|
|
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intel_engine_init_cmd_parser(engine);
|
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}
|
|
|
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int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
|
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{
|
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struct drm_i915_gem_object *obj;
|
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struct i915_vma *vma;
|
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int ret;
|
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|
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WARN_ON(engine->scratch);
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|
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obj = i915_gem_object_create_stolen(engine->i915, size);
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if (!obj)
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obj = i915_gem_object_create_internal(engine->i915, size);
|
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if (IS_ERR(obj)) {
|
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DRM_ERROR("Failed to allocate scratch page\n");
|
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return PTR_ERR(obj);
|
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}
|
|
|
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vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
|
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if (IS_ERR(vma)) {
|
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ret = PTR_ERR(vma);
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goto err_unref;
|
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}
|
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|
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ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH);
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if (ret)
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goto err_unref;
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|
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engine->scratch = vma;
|
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DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
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engine->name, i915_ggtt_offset(vma));
|
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return 0;
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|
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err_unref:
|
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i915_gem_object_put(obj);
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return ret;
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}
|
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|
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static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
|
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{
|
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i915_vma_unpin_and_release(&engine->scratch);
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}
|
|
|
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static void cleanup_phys_status_page(struct intel_engine_cs *engine)
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{
|
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struct drm_i915_private *dev_priv = engine->i915;
|
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|
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if (!dev_priv->status_page_dmah)
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return;
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|
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drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
|
|
engine->status_page.page_addr = NULL;
|
|
}
|
|
|
|
static void cleanup_status_page(struct intel_engine_cs *engine)
|
|
{
|
|
struct i915_vma *vma;
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
vma = fetch_and_zero(&engine->status_page.vma);
|
|
if (!vma)
|
|
return;
|
|
|
|
obj = vma->obj;
|
|
|
|
i915_vma_unpin(vma);
|
|
i915_vma_close(vma);
|
|
|
|
i915_gem_object_unpin_map(obj);
|
|
__i915_gem_object_release_unless_active(obj);
|
|
}
|
|
|
|
static int init_status_page(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_gem_object *obj;
|
|
struct i915_vma *vma;
|
|
unsigned int flags;
|
|
void *vaddr;
|
|
int ret;
|
|
|
|
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
|
|
if (IS_ERR(obj)) {
|
|
DRM_ERROR("Failed to allocate status page\n");
|
|
return PTR_ERR(obj);
|
|
}
|
|
|
|
ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
|
|
if (ret)
|
|
goto err;
|
|
|
|
vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
|
|
if (IS_ERR(vma)) {
|
|
ret = PTR_ERR(vma);
|
|
goto err;
|
|
}
|
|
|
|
flags = PIN_GLOBAL;
|
|
if (!HAS_LLC(engine->i915))
|
|
/* On g33, we cannot place HWS above 256MiB, so
|
|
* restrict its pinning to the low mappable arena.
|
|
* Though this restriction is not documented for
|
|
* gen4, gen5, or byt, they also behave similarly
|
|
* and hang if the HWS is placed at the top of the
|
|
* GTT. To generalise, it appears that all !llc
|
|
* platforms have issues with us placing the HWS
|
|
* above the mappable region (even though we never
|
|
* actually map it).
|
|
*/
|
|
flags |= PIN_MAPPABLE;
|
|
else
|
|
flags |= PIN_HIGH;
|
|
ret = i915_vma_pin(vma, 0, 4096, flags);
|
|
if (ret)
|
|
goto err;
|
|
|
|
vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
|
|
if (IS_ERR(vaddr)) {
|
|
ret = PTR_ERR(vaddr);
|
|
goto err_unpin;
|
|
}
|
|
|
|
engine->status_page.vma = vma;
|
|
engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
|
|
engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
|
|
|
|
DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
|
|
engine->name, i915_ggtt_offset(vma));
|
|
return 0;
|
|
|
|
err_unpin:
|
|
i915_vma_unpin(vma);
|
|
err:
|
|
i915_gem_object_put(obj);
|
|
return ret;
|
|
}
|
|
|
|
static int init_phys_status_page(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
GEM_BUG_ON(engine->id != RCS);
|
|
|
|
dev_priv->status_page_dmah =
|
|
drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
|
|
if (!dev_priv->status_page_dmah)
|
|
return -ENOMEM;
|
|
|
|
engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
|
|
memset(engine->status_page.page_addr, 0, PAGE_SIZE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* intel_engines_init_common - initialize cengine state which might require hw access
|
|
* @engine: Engine to initialize.
|
|
*
|
|
* Initializes @engine@ structure members shared between legacy and execlists
|
|
* submission modes which do require hardware access.
|
|
*
|
|
* Typcally done at later stages of submission mode specific engine setup.
|
|
*
|
|
* Returns zero on success or an error code on failure.
|
|
*/
|
|
int intel_engine_init_common(struct intel_engine_cs *engine)
|
|
{
|
|
struct intel_ring *ring;
|
|
int ret;
|
|
|
|
engine->set_default_submission(engine);
|
|
|
|
/* We may need to do things with the shrinker which
|
|
* require us to immediately switch back to the default
|
|
* context. This can cause a problem as pinning the
|
|
* default context also requires GTT space which may not
|
|
* be available. To avoid this we always pin the default
|
|
* context.
|
|
*/
|
|
ring = engine->context_pin(engine, engine->i915->kernel_context);
|
|
if (IS_ERR(ring))
|
|
return PTR_ERR(ring);
|
|
|
|
ret = intel_engine_init_breadcrumbs(engine);
|
|
if (ret)
|
|
goto err_unpin;
|
|
|
|
ret = i915_gem_render_state_init(engine);
|
|
if (ret)
|
|
goto err_breadcrumbs;
|
|
|
|
if (HWS_NEEDS_PHYSICAL(engine->i915))
|
|
ret = init_phys_status_page(engine);
|
|
else
|
|
ret = init_status_page(engine);
|
|
if (ret)
|
|
goto err_rs_fini;
|
|
|
|
return 0;
|
|
|
|
err_rs_fini:
|
|
i915_gem_render_state_fini(engine);
|
|
err_breadcrumbs:
|
|
intel_engine_fini_breadcrumbs(engine);
|
|
err_unpin:
|
|
engine->context_unpin(engine, engine->i915->kernel_context);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* intel_engines_cleanup_common - cleans up the engine state created by
|
|
* the common initiailizers.
|
|
* @engine: Engine to cleanup.
|
|
*
|
|
* This cleans up everything created by the common helpers.
|
|
*/
|
|
void intel_engine_cleanup_common(struct intel_engine_cs *engine)
|
|
{
|
|
intel_engine_cleanup_scratch(engine);
|
|
|
|
if (HWS_NEEDS_PHYSICAL(engine->i915))
|
|
cleanup_phys_status_page(engine);
|
|
else
|
|
cleanup_status_page(engine);
|
|
|
|
i915_gem_render_state_fini(engine);
|
|
intel_engine_fini_breadcrumbs(engine);
|
|
intel_engine_cleanup_cmd_parser(engine);
|
|
i915_gem_batch_pool_fini(&engine->batch_pool);
|
|
|
|
engine->context_unpin(engine, engine->i915->kernel_context);
|
|
}
|
|
|
|
u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
u64 acthd;
|
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
|
acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
|
|
RING_ACTHD_UDW(engine->mmio_base));
|
|
else if (INTEL_GEN(dev_priv) >= 4)
|
|
acthd = I915_READ(RING_ACTHD(engine->mmio_base));
|
|
else
|
|
acthd = I915_READ(ACTHD);
|
|
|
|
return acthd;
|
|
}
|
|
|
|
u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
u64 bbaddr;
|
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
|
bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
|
|
RING_BBADDR_UDW(engine->mmio_base));
|
|
else
|
|
bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
|
|
|
|
return bbaddr;
|
|
}
|
|
|
|
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
|
|
{
|
|
switch (type) {
|
|
case I915_CACHE_NONE: return " uncached";
|
|
case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
|
|
case I915_CACHE_L3_LLC: return " L3+LLC";
|
|
case I915_CACHE_WT: return " WT";
|
|
default: return "";
|
|
}
|
|
}
|
|
|
|
static inline uint32_t
|
|
read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
|
|
int subslice, i915_reg_t reg)
|
|
{
|
|
uint32_t mcr;
|
|
uint32_t ret;
|
|
enum forcewake_domains fw_domains;
|
|
|
|
fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
|
|
FW_REG_READ);
|
|
fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
|
|
GEN8_MCR_SELECTOR,
|
|
FW_REG_READ | FW_REG_WRITE);
|
|
|
|
spin_lock_irq(&dev_priv->uncore.lock);
|
|
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
|
|
|
|
mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
|
|
/*
|
|
* The HW expects the slice and sublice selectors to be reset to 0
|
|
* after reading out the registers.
|
|
*/
|
|
WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
|
|
mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
|
|
mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
|
|
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
|
|
|
|
ret = I915_READ_FW(reg);
|
|
|
|
mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
|
|
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
|
|
|
|
intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
|
|
spin_unlock_irq(&dev_priv->uncore.lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* NB: please notice the memset */
|
|
void intel_engine_get_instdone(struct intel_engine_cs *engine,
|
|
struct intel_instdone *instdone)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
u32 mmio_base = engine->mmio_base;
|
|
int slice;
|
|
int subslice;
|
|
|
|
memset(instdone, 0, sizeof(*instdone));
|
|
|
|
switch (INTEL_GEN(dev_priv)) {
|
|
default:
|
|
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
|
|
|
|
if (engine->id != RCS)
|
|
break;
|
|
|
|
instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
|
|
for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
|
|
instdone->sampler[slice][subslice] =
|
|
read_subslice_reg(dev_priv, slice, subslice,
|
|
GEN7_SAMPLER_INSTDONE);
|
|
instdone->row[slice][subslice] =
|
|
read_subslice_reg(dev_priv, slice, subslice,
|
|
GEN7_ROW_INSTDONE);
|
|
}
|
|
break;
|
|
case 7:
|
|
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
|
|
|
|
if (engine->id != RCS)
|
|
break;
|
|
|
|
instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
|
|
instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
|
|
instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
|
|
|
|
break;
|
|
case 6:
|
|
case 5:
|
|
case 4:
|
|
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
|
|
|
|
if (engine->id == RCS)
|
|
/* HACK: Using the wrong struct member */
|
|
instdone->slice_common = I915_READ(GEN4_INSTDONE1);
|
|
break;
|
|
case 3:
|
|
case 2:
|
|
instdone->instdone = I915_READ(GEN2_INSTDONE);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int wa_add(struct drm_i915_private *dev_priv,
|
|
i915_reg_t addr,
|
|
const u32 mask, const u32 val)
|
|
{
|
|
const u32 idx = dev_priv->workarounds.count;
|
|
|
|
if (WARN_ON(idx >= I915_MAX_WA_REGS))
|
|
return -ENOSPC;
|
|
|
|
dev_priv->workarounds.reg[idx].addr = addr;
|
|
dev_priv->workarounds.reg[idx].value = val;
|
|
dev_priv->workarounds.reg[idx].mask = mask;
|
|
|
|
dev_priv->workarounds.count++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define WA_REG(addr, mask, val) do { \
|
|
const int r = wa_add(dev_priv, (addr), (mask), (val)); \
|
|
if (r) \
|
|
return r; \
|
|
} while (0)
|
|
|
|
#define WA_SET_BIT_MASKED(addr, mask) \
|
|
WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
|
|
|
|
#define WA_CLR_BIT_MASKED(addr, mask) \
|
|
WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
|
|
|
|
#define WA_SET_FIELD_MASKED(addr, mask, value) \
|
|
WA_REG(addr, mask, _MASKED_FIELD(mask, value))
|
|
|
|
#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
|
|
#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
|
|
|
|
#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
|
|
|
|
static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
|
|
i915_reg_t reg)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
struct i915_workarounds *wa = &dev_priv->workarounds;
|
|
const uint32_t index = wa->hw_whitelist_count[engine->id];
|
|
|
|
if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
|
|
return -EINVAL;
|
|
|
|
WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
|
|
i915_mmio_reg_offset(reg));
|
|
wa->hw_whitelist_count[engine->id]++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gen8_init_workarounds(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
|
|
|
|
/* WaDisableAsyncFlipPerfMode:bdw,chv */
|
|
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
|
|
|
|
/* WaDisablePartialInstShootdown:bdw,chv */
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
|
|
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
|
|
|
|
/* Use Force Non-Coherent whenever executing a 3D context. This is a
|
|
* workaround for for a possible hang in the unlikely event a TLB
|
|
* invalidation occurs during a PSD flush.
|
|
*/
|
|
/* WaForceEnableNonCoherent:bdw,chv */
|
|
/* WaHdcDisableFetchWhenMasked:bdw,chv */
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
|
HDC_DONOT_FETCH_MEM_WHEN_MASKED |
|
|
HDC_FORCE_NON_COHERENT);
|
|
|
|
/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
|
|
* "The Hierarchical Z RAW Stall Optimization allows non-overlapping
|
|
* polygons in the same 8x4 pixel/sample area to be processed without
|
|
* stalling waiting for the earlier ones to write to Hierarchical Z
|
|
* buffer."
|
|
*
|
|
* This optimization is off by default for BDW and CHV; turn it on.
|
|
*/
|
|
WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
|
|
|
|
/* Wa4x4STCOptimizationDisable:bdw,chv */
|
|
WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
|
|
|
|
/*
|
|
* BSpec recommends 8x4 when MSAA is used,
|
|
* however in practice 16x4 seems fastest.
|
|
*
|
|
* Note that PS/WM thread counts depend on the WIZ hashing
|
|
* disable bit, which we don't touch here, but it's good
|
|
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
|
|
*/
|
|
WA_SET_FIELD_MASKED(GEN7_GT_MODE,
|
|
GEN6_WIZ_HASHING_MASK,
|
|
GEN6_WIZ_HASHING_16x4);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bdw_init_workarounds(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
int ret;
|
|
|
|
ret = gen8_init_workarounds(engine);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
|
|
|
|
/* WaDisableDopClockGating:bdw
|
|
*
|
|
* Also see the related UCGTCL1 write in broadwell_init_clock_gating()
|
|
* to disable EUTC clock gating.
|
|
*/
|
|
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
|
|
DOP_CLOCK_GATING_DISABLE);
|
|
|
|
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
|
|
GEN8_SAMPLER_POWER_BYPASS_DIS);
|
|
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
|
/* WaForceContextSaveRestoreNonCoherent:bdw */
|
|
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
|
|
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
|
|
(IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int chv_init_workarounds(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
int ret;
|
|
|
|
ret = gen8_init_workarounds(engine);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* WaDisableThreadStallDopClockGating:chv */
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
|
|
|
|
/* Improve HiZ throughput on CHV. */
|
|
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gen9_init_workarounds(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
int ret;
|
|
|
|
/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
|
|
I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
|
|
|
|
/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
|
|
I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
|
|
GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
|
|
|
|
/* WaDisableKillLogic:bxt,skl,kbl */
|
|
if (!IS_COFFEELAKE(dev_priv))
|
|
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
|
|
ECOCHK_DIS_TLB);
|
|
|
|
if (HAS_LLC(dev_priv)) {
|
|
/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
|
|
*
|
|
* Must match Display Engine. See
|
|
* WaCompressedResourceDisplayNewHashMode.
|
|
*/
|
|
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
|
|
GEN9_PBE_COMPRESSED_HASH_SELECTION);
|
|
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
|
|
GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
|
|
WA_SET_BIT(MMCD_MISC_CTRL, MMCD_PCLA | MMCD_HOTSPOT_EN);
|
|
}
|
|
|
|
/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
|
|
/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
|
|
FLOW_CONTROL_ENABLE |
|
|
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
|
|
|
|
/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
|
|
if (!IS_COFFEELAKE(dev_priv))
|
|
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
|
|
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
|
|
|
|
/* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
|
|
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
|
|
GEN9_DG_MIRROR_FIX_ENABLE);
|
|
|
|
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
|
|
WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
|
|
GEN9_RHWO_OPTIMIZATION_DISABLE);
|
|
/*
|
|
* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
|
|
* but we do that in per ctx batchbuffer as there is an issue
|
|
* with this register not getting restored on ctx restore
|
|
*/
|
|
}
|
|
|
|
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
|
|
/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
|
|
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
|
|
GEN9_ENABLE_YV12_BUGFIX |
|
|
GEN9_ENABLE_GPGPU_PREEMPTION);
|
|
|
|
/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
|
|
/* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
|
|
WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
|
|
GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
|
|
|
|
/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
|
|
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
|
|
GEN9_CCS_TLB_PREFETCH_ENABLE);
|
|
|
|
/* WaDisableMaskBasedCammingInRCC:bxt */
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
|
|
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
|
|
PIXEL_MASK_CAMMING_DISABLE);
|
|
|
|
/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
|
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
|
|
HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
|
|
|
|
/* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
|
|
* both tied to WaForceContextSaveRestoreNonCoherent
|
|
* in some hsds for skl. We keep the tie for all gen9. The
|
|
* documentation is a bit hazy and so we want to get common behaviour,
|
|
* even though there is no clear evidence we would need both on kbl/bxt.
|
|
* This area has been source of system hangs so we play it safe
|
|
* and mimic the skl regardless of what bspec says.
|
|
*
|
|
* Use Force Non-Coherent whenever executing a 3D context. This
|
|
* is a workaround for a possible hang in the unlikely event
|
|
* a TLB invalidation occurs during a PSD flush.
|
|
*/
|
|
|
|
/* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
|
HDC_FORCE_NON_COHERENT);
|
|
|
|
/* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
|
|
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
|
|
BDW_DISABLE_HDC_INVALIDATION);
|
|
|
|
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
|
|
if (IS_SKYLAKE(dev_priv) ||
|
|
IS_KABYLAKE(dev_priv) ||
|
|
IS_COFFEELAKE(dev_priv) ||
|
|
IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
|
|
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
|
|
GEN8_SAMPLER_POWER_BYPASS_DIS);
|
|
|
|
/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
|
|
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
|
|
|
|
/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
|
|
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
|
|
GEN8_LQSC_FLUSH_COHERENT_LINES));
|
|
|
|
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
|
|
ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */
|
|
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
|
|
ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
u8 vals[3] = { 0, 0, 0 };
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
u8 ss;
|
|
|
|
/*
|
|
* Only consider slices where one, and only one, subslice has 7
|
|
* EUs
|
|
*/
|
|
if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
|
|
continue;
|
|
|
|
/*
|
|
* subslice_7eu[i] != 0 (because of the check above) and
|
|
* ss_max == 4 (maximum number of subslices possible per slice)
|
|
*
|
|
* -> 0 <= ss <= 3;
|
|
*/
|
|
ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
|
|
vals[i] = 3 - ss;
|
|
}
|
|
|
|
if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
|
|
return 0;
|
|
|
|
/* Tune IZ hashing. See intel_device_info_runtime_init() */
|
|
WA_SET_FIELD_MASKED(GEN7_GT_MODE,
|
|
GEN9_IZ_HASHING_MASK(2) |
|
|
GEN9_IZ_HASHING_MASK(1) |
|
|
GEN9_IZ_HASHING_MASK(0),
|
|
GEN9_IZ_HASHING(2, vals[2]) |
|
|
GEN9_IZ_HASHING(1, vals[1]) |
|
|
GEN9_IZ_HASHING(0, vals[0]));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int skl_init_workarounds(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
int ret;
|
|
|
|
ret = gen9_init_workarounds(engine);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Actual WA is to disable percontext preemption granularity control
|
|
* until D0 which is the default case so this is equivalent to
|
|
* !WaDisablePerCtxtPreemptionGranularityControl:skl
|
|
*/
|
|
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
|
|
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
|
|
|
|
/* WaEnableGapsTsvCreditFix:skl */
|
|
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
|
|
GEN9_GAPS_TSV_CREDIT_DISABLE));
|
|
|
|
/* WaDisableGafsUnitClkGating:skl */
|
|
I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
|
|
GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
|
|
|
|
/* WaInPlaceDecompressionHang:skl */
|
|
if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
|
|
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
|
|
(I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
|
|
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
|
|
|
|
/* WaDisableLSQCROPERFforOCL:skl */
|
|
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return skl_tune_iz_hashing(engine);
|
|
}
|
|
|
|
static int bxt_init_workarounds(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
int ret;
|
|
|
|
ret = gen9_init_workarounds(engine);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* WaStoreMultiplePTEenable:bxt */
|
|
/* This is a requirement according to Hardware specification */
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
|
|
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
|
|
|
|
/* WaSetClckGatingDisableMedia:bxt */
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
|
|
I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
|
|
~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
|
|
}
|
|
|
|
/* WaDisableThreadStallDopClockGating:bxt */
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
|
|
STALL_DOP_GATING_DISABLE);
|
|
|
|
/* WaDisablePooledEuLoadBalancingFix:bxt */
|
|
if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
|
|
I915_WRITE(FF_SLICE_CS_CHICKEN2,
|
|
_MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
|
|
}
|
|
|
|
/* WaDisableSbeCacheDispatchPortSharing:bxt */
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
|
|
WA_SET_BIT_MASKED(
|
|
GEN7_HALF_SLICE_CHICKEN1,
|
|
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
|
|
}
|
|
|
|
/* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
|
|
/* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
|
|
/* WaDisableObjectLevelPreemtionForInstanceId:bxt */
|
|
/* WaDisableLSQCROPERFforOCL:bxt */
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
|
|
ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* WaProgramL3SqcReg1DefaultForPerf:bxt */
|
|
if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
|
|
I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
|
|
L3_HIGH_PRIO_CREDITS(2));
|
|
|
|
/* WaToEnableHwFixForPushConstHWBug:bxt */
|
|
if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
|
|
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
|
|
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
|
|
|
|
/* WaInPlaceDecompressionHang:bxt */
|
|
if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
|
|
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
|
|
(I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
|
|
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cnl_init_workarounds(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
int ret;
|
|
|
|
/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
|
|
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
|
|
I915_WRITE(GAMT_CHKN_BIT_REG,
|
|
(I915_READ(GAMT_CHKN_BIT_REG) |
|
|
GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT));
|
|
|
|
/* WaForceContextSaveRestoreNonCoherent:cnl */
|
|
WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
|
|
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
|
|
|
|
/* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
|
|
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
|
|
|
|
/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
|
|
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
|
|
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
|
|
|
|
/* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */
|
|
if (IS_CNL_REVID(dev_priv, 0, CNL_REVID_B0))
|
|
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
|
|
GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
|
|
|
|
/* WaInPlaceDecompressionHang:cnl */
|
|
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
|
|
(I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
|
|
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
|
|
|
|
/* WaPushConstantDereferenceHoldDisable:cnl */
|
|
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
|
|
|
|
/* FtrEnableFastAnisoL1BankingFix: cnl */
|
|
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
|
|
|
|
/* WaEnablePreemptionGranularityControlByUMD:cnl */
|
|
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kbl_init_workarounds(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
int ret;
|
|
|
|
ret = gen9_init_workarounds(engine);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* WaEnableGapsTsvCreditFix:kbl */
|
|
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
|
|
GEN9_GAPS_TSV_CREDIT_DISABLE));
|
|
|
|
/* WaDisableDynamicCreditSharing:kbl */
|
|
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
|
|
I915_WRITE(GAMT_CHKN_BIT_REG,
|
|
(I915_READ(GAMT_CHKN_BIT_REG) |
|
|
GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING));
|
|
|
|
/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
|
|
if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
|
HDC_FENCE_DEST_SLM_DISABLE);
|
|
|
|
/* WaToEnableHwFixForPushConstHWBug:kbl */
|
|
if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
|
|
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
|
|
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
|
|
|
|
/* WaDisableGafsUnitClkGating:kbl */
|
|
I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
|
|
GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
|
|
|
|
/* WaDisableSbeCacheDispatchPortSharing:kbl */
|
|
WA_SET_BIT_MASKED(
|
|
GEN7_HALF_SLICE_CHICKEN1,
|
|
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
|
|
|
|
/* WaInPlaceDecompressionHang:kbl */
|
|
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
|
|
(I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
|
|
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
|
|
|
|
/* WaDisableLSQCROPERFforOCL:kbl */
|
|
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int glk_init_workarounds(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
int ret;
|
|
|
|
ret = gen9_init_workarounds(engine);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* WaToEnableHwFixForPushConstHWBug:glk */
|
|
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
|
|
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cfl_init_workarounds(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
int ret;
|
|
|
|
ret = gen9_init_workarounds(engine);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* WaEnableGapsTsvCreditFix:cfl */
|
|
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
|
|
GEN9_GAPS_TSV_CREDIT_DISABLE));
|
|
|
|
/* WaToEnableHwFixForPushConstHWBug:cfl */
|
|
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
|
|
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
|
|
|
|
/* WaDisableGafsUnitClkGating:cfl */
|
|
I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
|
|
GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
|
|
|
|
/* WaDisableSbeCacheDispatchPortSharing:cfl */
|
|
WA_SET_BIT_MASKED(
|
|
GEN7_HALF_SLICE_CHICKEN1,
|
|
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
|
|
|
|
/* WaInPlaceDecompressionHang:cfl */
|
|
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
|
|
(I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
|
|
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
|
|
|
|
return 0;
|
|
}
|
|
|
|
int init_workarounds_ring(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
int err;
|
|
|
|
WARN_ON(engine->id != RCS);
|
|
|
|
dev_priv->workarounds.count = 0;
|
|
dev_priv->workarounds.hw_whitelist_count[engine->id] = 0;
|
|
|
|
if (IS_BROADWELL(dev_priv))
|
|
err = bdw_init_workarounds(engine);
|
|
else if (IS_CHERRYVIEW(dev_priv))
|
|
err = chv_init_workarounds(engine);
|
|
else if (IS_SKYLAKE(dev_priv))
|
|
err = skl_init_workarounds(engine);
|
|
else if (IS_BROXTON(dev_priv))
|
|
err = bxt_init_workarounds(engine);
|
|
else if (IS_KABYLAKE(dev_priv))
|
|
err = kbl_init_workarounds(engine);
|
|
else if (IS_GEMINILAKE(dev_priv))
|
|
err = glk_init_workarounds(engine);
|
|
else if (IS_COFFEELAKE(dev_priv))
|
|
err = cfl_init_workarounds(engine);
|
|
else if (IS_CANNONLAKE(dev_priv))
|
|
err = cnl_init_workarounds(engine);
|
|
else
|
|
err = 0;
|
|
if (err)
|
|
return err;
|
|
|
|
DRM_DEBUG_DRIVER("%s: Number of context specific w/a: %d\n",
|
|
engine->name, dev_priv->workarounds.count);
|
|
return 0;
|
|
}
|
|
|
|
int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
|
|
{
|
|
struct i915_workarounds *w = &req->i915->workarounds;
|
|
u32 *cs;
|
|
int ret, i;
|
|
|
|
if (w->count == 0)
|
|
return 0;
|
|
|
|
ret = req->engine->emit_flush(req, EMIT_BARRIER);
|
|
if (ret)
|
|
return ret;
|
|
|
|
cs = intel_ring_begin(req, (w->count * 2 + 2));
|
|
if (IS_ERR(cs))
|
|
return PTR_ERR(cs);
|
|
|
|
*cs++ = MI_LOAD_REGISTER_IMM(w->count);
|
|
for (i = 0; i < w->count; i++) {
|
|
*cs++ = i915_mmio_reg_offset(w->reg[i].addr);
|
|
*cs++ = w->reg[i].value;
|
|
}
|
|
*cs++ = MI_NOOP;
|
|
|
|
intel_ring_advance(req, cs);
|
|
|
|
ret = req->engine->emit_flush(req, EMIT_BARRIER);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool ring_is_idle(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
bool idle = true;
|
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
/* First check that no commands are left in the ring */
|
|
if ((I915_READ_HEAD(engine) & HEAD_ADDR) !=
|
|
(I915_READ_TAIL(engine) & TAIL_ADDR))
|
|
idle = false;
|
|
|
|
/* No bit for gen2, so assume the CS parser is idle */
|
|
if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
|
|
idle = false;
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
return idle;
|
|
}
|
|
|
|
/**
|
|
* intel_engine_is_idle() - Report if the engine has finished process all work
|
|
* @engine: the intel_engine_cs
|
|
*
|
|
* Return true if there are no requests pending, nothing left to be submitted
|
|
* to hardware, and that the engine is idle.
|
|
*/
|
|
bool intel_engine_is_idle(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
/* More white lies, if wedged, hw state is inconsistent */
|
|
if (i915_terminally_wedged(&dev_priv->gpu_error))
|
|
return true;
|
|
|
|
/* Any inflight/incomplete requests? */
|
|
if (!i915_seqno_passed(intel_engine_get_seqno(engine),
|
|
intel_engine_last_submit(engine)))
|
|
return false;
|
|
|
|
if (I915_SELFTEST_ONLY(engine->breadcrumbs.mock))
|
|
return true;
|
|
|
|
/* Interrupt/tasklet pending? */
|
|
if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted))
|
|
return false;
|
|
|
|
/* Both ports drained, no more ELSP submission? */
|
|
if (port_request(&engine->execlists.port[0]))
|
|
return false;
|
|
|
|
/* ELSP is empty, but there are ready requests? */
|
|
if (READ_ONCE(engine->execlists.first))
|
|
return false;
|
|
|
|
/* Ring stopped? */
|
|
if (!ring_is_idle(engine))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
bool intel_engines_are_idle(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
|
|
if (READ_ONCE(dev_priv->gt.active_requests))
|
|
return false;
|
|
|
|
/* If the driver is wedged, HW state may be very inconsistent and
|
|
* report that it is still busy, even though we have stopped using it.
|
|
*/
|
|
if (i915_terminally_wedged(&dev_priv->gpu_error))
|
|
return true;
|
|
|
|
for_each_engine(engine, dev_priv, id) {
|
|
if (!intel_engine_is_idle(engine))
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
void intel_engines_reset_default_submission(struct drm_i915_private *i915)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
|
|
for_each_engine(engine, i915, id)
|
|
engine->set_default_submission(engine);
|
|
}
|
|
|
|
void intel_engines_mark_idle(struct drm_i915_private *i915)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
|
|
for_each_engine(engine, i915, id) {
|
|
intel_engine_disarm_breadcrumbs(engine);
|
|
i915_gem_batch_pool_fini(&engine->batch_pool);
|
|
tasklet_kill(&engine->execlists.irq_tasklet);
|
|
engine->execlists.no_priolist = false;
|
|
}
|
|
}
|
|
|
|
bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
|
|
{
|
|
switch (INTEL_GEN(engine->i915)) {
|
|
case 2:
|
|
return false; /* uses physical not virtual addresses */
|
|
case 3:
|
|
/* maybe only uses physical not virtual addresses */
|
|
return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
|
|
case 6:
|
|
return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
|
|
default:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
|
|
#include "selftests/mock_engine.c"
|
|
#endif
|