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![Michal Wajdeczko](/assets/img/avatar_default.png)
Our global struct with params is named exactly the same way as new preferred name for the drm_i915_private function parameter. To avoid such name reuse lets use different name for the global. v5: pure rename v6: fix Credits-to: Coccinelle @@ identifier n; @@ ( - i915.n + i915_modparams.n ) Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170919193846.38060-1-michal.wajdeczko@intel.com
420 lines
13 KiB
C
420 lines
13 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Vinit Azad <vinit.azad@intel.com>
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* Ben Widawsky <ben@bwidawsk.net>
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* Dave Gordon <david.s.gordon@intel.com>
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* Alex Dai <yu.dai@intel.com>
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*/
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#include "i915_drv.h"
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#include "intel_uc.h"
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/**
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* DOC: GuC-specific firmware loader
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*
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* intel_guc:
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* Top level structure of guc. It handles firmware loading and manages client
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* pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
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* ExecList submission.
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*
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* Firmware versioning:
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* The firmware build process will generate a version header file with major and
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* minor version defined. The versions are built into CSS header of firmware.
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* i915 kernel driver set the minimal firmware version required per platform.
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* The firmware installation package will install (symbolic link) proper version
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* of firmware.
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*
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* GuC address space:
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* GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
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* which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
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* 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
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* used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
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*
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*/
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#define SKL_FW_MAJOR 6
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#define SKL_FW_MINOR 1
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#define BXT_FW_MAJOR 8
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#define BXT_FW_MINOR 7
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#define KBL_FW_MAJOR 9
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#define KBL_FW_MINOR 14
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#define GLK_FW_MAJOR 10
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#define GLK_FW_MINOR 56
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#define GUC_FW_PATH(platform, major, minor) \
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"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
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#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
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MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
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#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
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MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
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#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
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MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
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#define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR)
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static u32 get_gttype(struct drm_i915_private *dev_priv)
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{
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/* XXX: GT type based on PCI device ID? field seems unused by fw */
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return 0;
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}
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static u32 get_core_family(struct drm_i915_private *dev_priv)
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{
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u32 gen = INTEL_GEN(dev_priv);
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switch (gen) {
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case 9:
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return GUC_CORE_FAMILY_GEN9;
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default:
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MISSING_CASE(gen);
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return GUC_CORE_FAMILY_UNKNOWN;
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}
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}
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/*
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* Initialise the GuC parameter block before starting the firmware
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* transfer. These parameters are read by the firmware on startup
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* and cannot be changed thereafter.
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*/
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static void guc_params_init(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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u32 params[GUC_CTL_MAX_DWORDS];
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int i;
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memset(¶ms, 0, sizeof(params));
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params[GUC_CTL_DEVICE_INFO] |=
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(get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
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(get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
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/*
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* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
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* second. This ARAR is calculated by:
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* Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
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*/
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params[GUC_CTL_ARAT_HIGH] = 0;
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params[GUC_CTL_ARAT_LOW] = 100000000;
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params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
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params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
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GUC_CTL_VCS2_ENABLED;
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params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
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if (i915_modparams.guc_log_level >= 0) {
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params[GUC_CTL_DEBUG] =
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i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
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} else
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params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
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/* If GuC submission is enabled, set up additional parameters here */
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if (i915_modparams.enable_guc_submission) {
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u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
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u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
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u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
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params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
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params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
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pgs >>= PAGE_SHIFT;
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params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
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(ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
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params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
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/* Unmask this bit to enable the GuC's internal scheduler */
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params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
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}
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I915_WRITE(SOFT_SCRATCH(0), 0);
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for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
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I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
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}
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/*
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* Read the GuC status register (GUC_STATUS) and store it in the
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* specified location; then return a boolean indicating whether
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* the value matches either of two values representing completion
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* of the GuC boot process.
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*
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* This is used for polling the GuC status in a wait_for()
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* loop below.
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*/
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static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
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u32 *status)
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{
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u32 val = I915_READ(GUC_STATUS);
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u32 uk_val = val & GS_UKERNEL_MASK;
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*status = val;
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return (uk_val == GS_UKERNEL_READY ||
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((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
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}
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/*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* Architecturally, the DMA engine is bidirectional, and can potentially even
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* transfer between GTT locations. This functionality is left out of the API
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* for now as there is no need for it.
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*
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* Note that GuC needs the CSS header plus uKernel code to be copied by the
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* DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
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*/
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static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
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struct i915_vma *vma)
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{
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struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
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unsigned long offset;
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struct sg_table *sg = vma->pages;
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u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
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int i, ret = 0;
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/* where RSA signature starts */
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offset = guc_fw->rsa_offset;
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/* Copy RSA signature from the fw image to HW for verification */
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sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
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for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
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I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
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/* The header plus uCode will be copied to WOPCM via DMA, excluding any
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* other components */
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I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
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/* Set the source address for the new blob */
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offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
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I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
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I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
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/*
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* Set the DMA destination. Current uCode expects the code to be
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* loaded at 8k; locations below this are used for the stack.
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*/
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I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
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I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
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/* Finally start the DMA */
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I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
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/*
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* Wait for the DMA to complete & the GuC to start up.
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* NB: Docs recommend not using the interrupt for completion.
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* Measurements indicate this should take no more than 20ms, so a
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* timeout here indicates that the GuC has failed and is unusable.
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* (Higher levels of the driver will attempt to fall back to
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* execlist mode if this happens.)
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*/
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ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
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DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
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I915_READ(DMA_CTRL), status);
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if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
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DRM_ERROR("GuC firmware signature verification failed\n");
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ret = -ENOEXEC;
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}
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DRM_DEBUG_DRIVER("returning %d\n", ret);
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return ret;
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}
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u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
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{
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u32 wopcm_size = GUC_WOPCM_TOP;
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/* On BXT, the top of WOPCM is reserved for RC6 context */
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if (IS_GEN9_LP(dev_priv))
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wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
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return wopcm_size;
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}
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/*
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* Load the GuC firmware blob into the MinuteIA.
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*/
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static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
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{
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struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
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struct i915_vma *vma;
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int ret;
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ret = i915_gem_object_set_to_gtt_domain(guc_fw->obj, false);
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if (ret) {
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DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
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return ret;
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}
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vma = i915_gem_object_ggtt_pin(guc_fw->obj, NULL, 0, 0,
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PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
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if (IS_ERR(vma)) {
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DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
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return PTR_ERR(vma);
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}
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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/* Enable MIA caching. GuC clock gating is disabled. */
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I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
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/* WaDisableMinuteIaClockGating:bxt */
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if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
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I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
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~GUC_ENABLE_MIA_CLOCK_GATING));
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}
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/* WaC6DisallowByGfxPause:bxt */
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if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
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I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
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if (IS_GEN9_LP(dev_priv))
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I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
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else
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I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
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if (IS_GEN9(dev_priv)) {
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/* DOP Clock Gating Enable for GuC clocks */
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I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
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I915_READ(GEN7_MISCCPCTL)));
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/* allows for 5us (in 10ns units) before GT can go to RC6 */
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I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
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}
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guc_params_init(dev_priv);
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ret = guc_ucode_xfer_dma(dev_priv, vma);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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/*
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* We keep the object pages for reuse during resume. But we can unpin it
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* now that DMA has completed, so it doesn't continue to take up space.
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*/
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i915_vma_unpin(vma);
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return ret;
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}
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/**
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* intel_guc_init_hw() - finish preparing the GuC for activity
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* @guc: intel_guc structure
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*
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* Called during driver loading and also after a GPU reset.
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*
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* The main action required here it to load the GuC uCode into the device.
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* The firmware image should have already been fetched into memory by the
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* earlier call to intel_guc_init(), so here we need only check that
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* worked, and then transfer the image to the h/w.
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*
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* Return: non-zero code on error
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*/
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int intel_guc_init_hw(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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const char *fw_path = guc->fw.path;
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int ret;
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DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
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fw_path,
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intel_uc_fw_status_repr(guc->fw.fetch_status),
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intel_uc_fw_status_repr(guc->fw.load_status));
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if (guc->fw.fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
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return -EIO;
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guc->fw.load_status = INTEL_UC_FIRMWARE_PENDING;
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DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
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intel_uc_fw_status_repr(guc->fw.fetch_status),
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intel_uc_fw_status_repr(guc->fw.load_status));
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ret = guc_ucode_xfer(dev_priv);
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if (ret)
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return -EAGAIN;
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guc->fw.load_status = INTEL_UC_FIRMWARE_SUCCESS;
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DRM_INFO("GuC %s (firmware %s [version %u.%u])\n",
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i915_modparams.enable_guc_submission ? "submission enabled" :
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"loaded",
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guc->fw.path,
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guc->fw.major_ver_found, guc->fw.minor_ver_found);
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return 0;
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}
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/**
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* intel_guc_select_fw() - selects GuC firmware for loading
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* @guc: intel_guc struct
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*
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* Return: zero when we know firmware, non-zero in other case
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*/
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int intel_guc_select_fw(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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guc->fw.path = NULL;
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guc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
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guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
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guc->fw.type = INTEL_UC_FW_TYPE_GUC;
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if (i915_modparams.guc_firmware_path) {
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guc->fw.path = i915_modparams.guc_firmware_path;
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guc->fw.major_ver_wanted = 0;
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guc->fw.minor_ver_wanted = 0;
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} else if (IS_SKYLAKE(dev_priv)) {
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guc->fw.path = I915_SKL_GUC_UCODE;
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guc->fw.major_ver_wanted = SKL_FW_MAJOR;
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guc->fw.minor_ver_wanted = SKL_FW_MINOR;
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} else if (IS_BROXTON(dev_priv)) {
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guc->fw.path = I915_BXT_GUC_UCODE;
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guc->fw.major_ver_wanted = BXT_FW_MAJOR;
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guc->fw.minor_ver_wanted = BXT_FW_MINOR;
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} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
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guc->fw.path = I915_KBL_GUC_UCODE;
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guc->fw.major_ver_wanted = KBL_FW_MAJOR;
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guc->fw.minor_ver_wanted = KBL_FW_MINOR;
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} else if (IS_GEMINILAKE(dev_priv)) {
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guc->fw.path = I915_GLK_GUC_UCODE;
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guc->fw.major_ver_wanted = GLK_FW_MAJOR;
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guc->fw.minor_ver_wanted = GLK_FW_MINOR;
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} else {
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DRM_ERROR("No GuC firmware known for platform with GuC!\n");
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return -ENOENT;
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}
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return 0;
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}
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