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![Chris Wilson](/assets/img/avatar_default.png)
After initiating a sideband transaction, we only want to wait for the transaction to become idle. If, as we are, we wait for both the busy and error flag to clear, if an error is raised we just spin until the timeout. Once the hw is idle, we can then check to see if the hw flagged an error, and report it distinctly. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170223141020.13250-1-chris@chris-wilson.co.uk Reviewed-by: Jani Nikula <jani.nikula@intel.com>
295 lines
7.7 KiB
C
295 lines
7.7 KiB
C
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "i915_drv.h"
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#include "intel_drv.h"
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/*
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* IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
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* VLV_VLV2_PUNIT_HAS_0.8.docx
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*/
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/* Standard MMIO read, non-posted */
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#define SB_MRD_NP 0x00
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/* Standard MMIO write, non-posted */
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#define SB_MWR_NP 0x01
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/* Private register read, double-word addressing, non-posted */
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#define SB_CRRDDA_NP 0x06
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/* Private register write, double-word addressing, non-posted */
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#define SB_CRWRDA_NP 0x07
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static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
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u32 port, u32 opcode, u32 addr, u32 *val)
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{
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u32 cmd, be = 0xf, bar = 0;
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bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
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cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
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(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
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(bar << IOSF_BAR_SHIFT);
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WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
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if (intel_wait_for_register(dev_priv,
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VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
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5)) {
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DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
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is_read ? "read" : "write");
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return -EAGAIN;
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}
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I915_WRITE(VLV_IOSF_ADDR, addr);
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I915_WRITE(VLV_IOSF_DATA, is_read ? 0 : *val);
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I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
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if (intel_wait_for_register(dev_priv,
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VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
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5)) {
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DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
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is_read ? "read" : "write");
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return -ETIMEDOUT;
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}
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if (is_read)
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*val = I915_READ(VLV_IOSF_DATA);
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return 0;
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}
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u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
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{
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u32 val = 0;
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WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
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mutex_lock(&dev_priv->sb_lock);
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vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
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SB_CRRDDA_NP, addr, &val);
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mutex_unlock(&dev_priv->sb_lock);
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return val;
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}
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int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
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{
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int err;
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WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
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mutex_lock(&dev_priv->sb_lock);
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err = vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
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SB_CRWRDA_NP, addr, &val);
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mutex_unlock(&dev_priv->sb_lock);
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return err;
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}
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u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
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{
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vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
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SB_CRWRDA_NP, reg, &val);
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}
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u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
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{
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u32 val = 0;
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WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
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mutex_lock(&dev_priv->sb_lock);
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vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
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SB_CRRDDA_NP, addr, &val);
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mutex_unlock(&dev_priv->sb_lock);
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return val;
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}
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u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
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u8 port, u32 reg, u32 val)
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{
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vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
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SB_CRWRDA_NP, reg, &val);
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}
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u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
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{
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vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
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SB_CRWRDA_NP, reg, &val);
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}
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u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
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{
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vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
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SB_CRWRDA_NP, reg, &val);
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}
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u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
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{
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u32 val = 0;
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vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
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SB_MRD_NP, reg, &val);
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/*
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* FIXME: There might be some registers where all 1's is a valid value,
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* so ideally we should check the register offset instead...
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*/
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WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
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pipe_name(pipe), reg, val);
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return val;
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}
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void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
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{
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vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
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SB_MWR_NP, reg, &val);
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}
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/* SBI access */
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u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
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enum intel_sbi_destination destination)
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{
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u32 value = 0;
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WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
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if (intel_wait_for_register(dev_priv,
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SBI_CTL_STAT, SBI_BUSY, 0,
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100)) {
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DRM_ERROR("timeout waiting for SBI to become ready\n");
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return 0;
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}
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I915_WRITE(SBI_ADDR, (reg << 16));
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I915_WRITE(SBI_DATA, 0);
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if (destination == SBI_ICLK)
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value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
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else
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value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
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I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
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if (intel_wait_for_register(dev_priv,
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SBI_CTL_STAT,
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SBI_BUSY,
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0,
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100)) {
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DRM_ERROR("timeout waiting for SBI to complete read\n");
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return 0;
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}
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if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
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DRM_ERROR("error during SBI read of reg %x\n", reg);
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return 0;
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}
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return I915_READ(SBI_DATA);
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}
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void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
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enum intel_sbi_destination destination)
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{
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u32 tmp;
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WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
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if (intel_wait_for_register(dev_priv,
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SBI_CTL_STAT, SBI_BUSY, 0,
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100)) {
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DRM_ERROR("timeout waiting for SBI to become ready\n");
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return;
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}
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I915_WRITE(SBI_ADDR, (reg << 16));
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I915_WRITE(SBI_DATA, value);
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if (destination == SBI_ICLK)
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tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
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else
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tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
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I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
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if (intel_wait_for_register(dev_priv,
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SBI_CTL_STAT,
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SBI_BUSY,
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0,
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100)) {
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DRM_ERROR("timeout waiting for SBI to complete write\n");
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return;
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}
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if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
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DRM_ERROR("error during SBI write of %x to reg %x\n",
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value, reg);
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return;
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}
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}
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u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
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reg, &val);
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return val;
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}
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void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
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{
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vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
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reg, &val);
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}
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