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synced 2024-08-25 10:19:47 +00:00
![Michal Wajdeczko](/assets/img/avatar_default.png)
Our global struct with params is named exactly the same way as new preferred name for the drm_i915_private function parameter. To avoid such name reuse lets use different name for the global. v5: pure rename v6: fix Credits-to: Coccinelle @@ identifier n; @@ ( - i915.n + i915_modparams.n ) Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170919193846.38060-1-michal.wajdeczko@intel.com
540 lines
14 KiB
C
540 lines
14 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "i915_drv.h"
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#include "intel_uc.h"
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#include <linux/firmware.h>
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/* Cleans up uC firmware by releasing the firmware GEM obj.
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*/
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static void __intel_uc_fw_fini(struct intel_uc_fw *uc_fw)
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{
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struct drm_i915_gem_object *obj;
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obj = fetch_and_zero(&uc_fw->obj);
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if (obj)
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i915_gem_object_put(obj);
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uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
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}
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/* Reset GuC providing us with fresh state for both GuC and HuC.
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*/
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static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
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{
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int ret;
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u32 guc_status;
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ret = intel_guc_reset(dev_priv);
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if (ret) {
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DRM_ERROR("GuC reset failed, ret = %d\n", ret);
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return ret;
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}
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guc_status = I915_READ(GUC_STATUS);
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WARN(!(guc_status & GS_MIA_IN_RESET),
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"GuC status: 0x%x, MIA core expected to be in reset\n",
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guc_status);
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return ret;
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}
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void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
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{
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if (!HAS_GUC(dev_priv)) {
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if (i915_modparams.enable_guc_loading > 0 ||
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i915_modparams.enable_guc_submission > 0)
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DRM_INFO("Ignoring GuC options, no hardware\n");
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i915_modparams.enable_guc_loading = 0;
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i915_modparams.enable_guc_submission = 0;
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return;
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}
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/* A negative value means "use platform default" */
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if (i915_modparams.enable_guc_loading < 0)
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i915_modparams.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
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/* Verify firmware version */
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if (i915_modparams.enable_guc_loading) {
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if (HAS_HUC_UCODE(dev_priv))
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intel_huc_select_fw(&dev_priv->huc);
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if (intel_guc_select_fw(&dev_priv->guc))
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i915_modparams.enable_guc_loading = 0;
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}
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/* Can't enable guc submission without guc loaded */
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if (!i915_modparams.enable_guc_loading)
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i915_modparams.enable_guc_submission = 0;
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/* A negative value means "use platform default" */
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if (i915_modparams.enable_guc_submission < 0)
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i915_modparams.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
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}
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static void gen8_guc_raise_irq(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
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}
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void intel_uc_init_early(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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intel_guc_ct_init_early(&guc->ct);
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mutex_init(&guc->send_mutex);
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guc->send = intel_guc_send_nop;
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guc->notify = gen8_guc_raise_irq;
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}
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static void fetch_uc_fw(struct drm_i915_private *dev_priv,
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struct intel_uc_fw *uc_fw)
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{
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struct pci_dev *pdev = dev_priv->drm.pdev;
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struct drm_i915_gem_object *obj;
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const struct firmware *fw = NULL;
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struct uc_css_header *css;
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size_t size;
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int err;
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if (!uc_fw->path)
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return;
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uc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
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DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
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intel_uc_fw_status_repr(uc_fw->fetch_status));
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err = request_firmware(&fw, uc_fw->path, &pdev->dev);
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if (err)
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goto fail;
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if (!fw)
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goto fail;
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DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
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uc_fw->path, fw);
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/* Check the size of the blob before examining buffer contents */
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if (fw->size < sizeof(struct uc_css_header)) {
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DRM_NOTE("Firmware header is missing\n");
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goto fail;
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}
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css = (struct uc_css_header *)fw->data;
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/* Firmware bits always start from header */
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uc_fw->header_offset = 0;
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uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
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css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
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if (uc_fw->header_size != sizeof(struct uc_css_header)) {
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DRM_NOTE("CSS header definition mismatch\n");
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goto fail;
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}
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/* then, uCode */
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uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
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uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
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/* now RSA */
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if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
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DRM_NOTE("RSA key size is bad\n");
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goto fail;
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}
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uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
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uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
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/* At least, it should have header, uCode and RSA. Size of all three. */
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size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
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if (fw->size < size) {
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DRM_NOTE("Missing firmware components\n");
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goto fail;
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}
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/*
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* The GuC firmware image has the version number embedded at a
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* well-known offset within the firmware blob; note that major / minor
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* version are TWO bytes each (i.e. u16), although all pointers and
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* offsets are defined in terms of bytes (u8).
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*/
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switch (uc_fw->type) {
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case INTEL_UC_FW_TYPE_GUC:
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/* Header and uCode will be loaded to WOPCM. Size of the two. */
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size = uc_fw->header_size + uc_fw->ucode_size;
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/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
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if (size > intel_guc_wopcm_size(dev_priv)) {
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DRM_ERROR("Firmware is too large to fit in WOPCM\n");
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goto fail;
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}
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uc_fw->major_ver_found = css->guc.sw_version >> 16;
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uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF;
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break;
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case INTEL_UC_FW_TYPE_HUC:
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uc_fw->major_ver_found = css->huc.sw_version >> 16;
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uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF;
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break;
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default:
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DRM_ERROR("Unknown firmware type %d\n", uc_fw->type);
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err = -ENOEXEC;
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goto fail;
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}
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if (uc_fw->major_ver_wanted == 0 && uc_fw->minor_ver_wanted == 0) {
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DRM_NOTE("Skipping %s firmware version check\n",
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intel_uc_fw_type_repr(uc_fw->type));
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} else if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
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uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
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DRM_NOTE("%s firmware version %d.%d, required %d.%d\n",
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intel_uc_fw_type_repr(uc_fw->type),
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uc_fw->major_ver_found, uc_fw->minor_ver_found,
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uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
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err = -ENOEXEC;
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goto fail;
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}
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DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
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uc_fw->major_ver_found, uc_fw->minor_ver_found,
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uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
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obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
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if (IS_ERR(obj)) {
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err = PTR_ERR(obj);
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goto fail;
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}
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uc_fw->obj = obj;
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uc_fw->size = fw->size;
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DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
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uc_fw->obj);
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release_firmware(fw);
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uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS;
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return;
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fail:
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DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
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uc_fw->path, err);
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DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
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err, fw, uc_fw->obj);
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release_firmware(fw); /* OK even if fw is NULL */
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uc_fw->fetch_status = INTEL_UC_FIRMWARE_FAIL;
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}
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void intel_uc_init_fw(struct drm_i915_private *dev_priv)
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{
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fetch_uc_fw(dev_priv, &dev_priv->huc.fw);
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fetch_uc_fw(dev_priv, &dev_priv->guc.fw);
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}
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void intel_uc_fini_fw(struct drm_i915_private *dev_priv)
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{
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__intel_uc_fw_fini(&dev_priv->guc.fw);
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__intel_uc_fw_fini(&dev_priv->huc.fw);
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}
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static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
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{
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GEM_BUG_ON(!guc->send_regs.base);
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GEM_BUG_ON(!guc->send_regs.count);
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GEM_BUG_ON(i >= guc->send_regs.count);
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return _MMIO(guc->send_regs.base + 4 * i);
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}
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static void guc_init_send_regs(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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enum forcewake_domains fw_domains = 0;
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unsigned int i;
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guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
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guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
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for (i = 0; i < guc->send_regs.count; i++) {
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fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
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guc_send_reg(guc, i),
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FW_REG_READ | FW_REG_WRITE);
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}
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guc->send_regs.fw_domains = fw_domains;
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}
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static void guc_capture_load_err_log(struct intel_guc *guc)
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{
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if (!guc->log.vma || i915_modparams.guc_log_level < 0)
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return;
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if (!guc->load_err_log)
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guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
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return;
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}
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static void guc_free_load_err_log(struct intel_guc *guc)
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{
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if (guc->load_err_log)
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i915_gem_object_put(guc->load_err_log);
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}
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static int guc_enable_communication(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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guc_init_send_regs(guc);
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if (HAS_GUC_CT(dev_priv))
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return intel_guc_enable_ct(guc);
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guc->send = intel_guc_send_mmio;
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return 0;
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}
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static void guc_disable_communication(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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if (HAS_GUC_CT(dev_priv))
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intel_guc_disable_ct(guc);
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guc->send = intel_guc_send_nop;
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}
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int intel_uc_init_hw(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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int ret, attempts;
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if (!i915_modparams.enable_guc_loading)
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return 0;
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guc_disable_communication(guc);
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gen9_reset_guc_interrupts(dev_priv);
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/* We need to notify the guc whenever we change the GGTT */
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i915_ggtt_enable_guc(dev_priv);
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if (i915_modparams.enable_guc_submission) {
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/*
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* This is stuff we need to have available at fw load time
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* if we are planning to enable submission later
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*/
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ret = i915_guc_submission_init(dev_priv);
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if (ret)
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goto err_guc;
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}
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/* init WOPCM */
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I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
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I915_WRITE(DMA_GUC_WOPCM_OFFSET,
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GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
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/* WaEnableuKernelHeaderValidFix:skl */
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/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
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if (IS_GEN9(dev_priv))
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attempts = 3;
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else
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attempts = 1;
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while (attempts--) {
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/*
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* Always reset the GuC just before (re)loading, so
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* that the state and timing are fairly predictable
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*/
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ret = __intel_uc_reset_hw(dev_priv);
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if (ret)
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goto err_submission;
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intel_huc_init_hw(&dev_priv->huc);
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ret = intel_guc_init_hw(&dev_priv->guc);
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if (ret == 0 || ret != -EAGAIN)
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break;
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DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
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"retry %d more time(s)\n", ret, attempts);
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}
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/* Did we succeded or run out of retries? */
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if (ret)
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goto err_log_capture;
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ret = guc_enable_communication(guc);
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if (ret)
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goto err_log_capture;
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intel_guc_auth_huc(dev_priv);
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if (i915_modparams.enable_guc_submission) {
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if (i915_modparams.guc_log_level >= 0)
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gen9_enable_guc_interrupts(dev_priv);
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ret = i915_guc_submission_enable(dev_priv);
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if (ret)
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goto err_interrupts;
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}
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return 0;
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/*
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* We've failed to load the firmware :(
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*
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* Decide whether to disable GuC submission and fall back to
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* execlist mode, and whether to hide the error by returning
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* zero or to return -EIO, which the caller will treat as a
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* nonfatal error (i.e. it doesn't prevent driver load, but
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* marks the GPU as wedged until reset).
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*/
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err_interrupts:
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guc_disable_communication(guc);
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gen9_disable_guc_interrupts(dev_priv);
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err_log_capture:
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guc_capture_load_err_log(guc);
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err_submission:
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if (i915_modparams.enable_guc_submission)
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i915_guc_submission_fini(dev_priv);
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err_guc:
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i915_ggtt_disable_guc(dev_priv);
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DRM_ERROR("GuC init failed\n");
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if (i915_modparams.enable_guc_loading > 1 ||
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i915_modparams.enable_guc_submission > 1)
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ret = -EIO;
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else
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ret = 0;
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if (i915_modparams.enable_guc_submission) {
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i915_modparams.enable_guc_submission = 0;
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DRM_NOTE("Falling back from GuC submission to execlist mode\n");
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}
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i915_modparams.enable_guc_loading = 0;
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DRM_NOTE("GuC firmware loading disabled\n");
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return ret;
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}
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void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
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{
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guc_free_load_err_log(&dev_priv->guc);
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if (!i915_modparams.enable_guc_loading)
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return;
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if (i915_modparams.enable_guc_submission)
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i915_guc_submission_disable(dev_priv);
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guc_disable_communication(&dev_priv->guc);
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if (i915_modparams.enable_guc_submission) {
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gen9_disable_guc_interrupts(dev_priv);
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i915_guc_submission_fini(dev_priv);
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}
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|
|
|
i915_ggtt_disable_guc(dev_priv);
|
|
}
|
|
|
|
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
|
|
{
|
|
WARN(1, "Unexpected send: action=%#x\n", *action);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*
|
|
* This function implements the MMIO based host to GuC interface.
|
|
*/
|
|
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
|
|
{
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
u32 status;
|
|
int i;
|
|
int ret;
|
|
|
|
GEM_BUG_ON(!len);
|
|
GEM_BUG_ON(len > guc->send_regs.count);
|
|
|
|
/* If CT is available, we expect to use MMIO only during init/fini */
|
|
GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
|
|
*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
|
|
*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
|
|
|
|
mutex_lock(&guc->send_mutex);
|
|
intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
|
|
|
|
for (i = 0; i < len; i++)
|
|
I915_WRITE(guc_send_reg(guc, i), action[i]);
|
|
|
|
POSTING_READ(guc_send_reg(guc, i - 1));
|
|
|
|
intel_guc_notify(guc);
|
|
|
|
/*
|
|
* No GuC command should ever take longer than 10ms.
|
|
* Fast commands should still complete in 10us.
|
|
*/
|
|
ret = __intel_wait_for_register_fw(dev_priv,
|
|
guc_send_reg(guc, 0),
|
|
INTEL_GUC_RECV_MASK,
|
|
INTEL_GUC_RECV_MASK,
|
|
10, 10, &status);
|
|
if (status != INTEL_GUC_STATUS_SUCCESS) {
|
|
/*
|
|
* Either the GuC explicitly returned an error (which
|
|
* we convert to -EIO here) or no response at all was
|
|
* received within the timeout limit (-ETIMEDOUT)
|
|
*/
|
|
if (ret != -ETIMEDOUT)
|
|
ret = -EIO;
|
|
|
|
DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
|
|
" ret=%d status=0x%08X response=0x%08X\n",
|
|
action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
|
|
}
|
|
|
|
intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
|
|
mutex_unlock(&guc->send_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int intel_guc_sample_forcewake(struct intel_guc *guc)
|
|
{
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
u32 action[2];
|
|
|
|
action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
|
|
/* WaRsDisableCoarsePowerGating:skl,bxt */
|
|
if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
|
|
action[1] = 0;
|
|
else
|
|
/* bit 0 and 1 are for Render and Media domain separately */
|
|
action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
|
|
|
|
return intel_guc_send(guc, action, ARRAY_SIZE(action));
|
|
}
|