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![Yang Zhang](/assets/img/avatar_default.png)
We already know the trigger mode of a given interrupt when programming the ioapice entry. So it's not necessary to set it in each interrupt delivery. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Reviewed-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
603 lines
15 KiB
C
603 lines
15 KiB
C
/*
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* Copyright (C) 2001 MandrakeSoft S.A.
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* Copyright 2010 Red Hat, Inc. and/or its affiliates.
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*
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* MandrakeSoft S.A.
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* 43, rue d'Aboukir
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* 75002 Paris - France
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* http://www.linux-mandrake.com/
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* http://www.mandrakesoft.com/
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Yunhong Jiang <yunhong.jiang@intel.com>
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* Yaozu (Eddie) Dong <eddie.dong@intel.com>
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* Based on Xen 3.1 code.
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*/
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#include <linux/kvm_host.h>
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#include <linux/kvm.h>
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#include <linux/mm.h>
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#include <linux/highmem.h>
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#include <linux/smp.h>
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#include <linux/hrtimer.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/current.h>
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#include <trace/events/kvm.h>
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#include "ioapic.h"
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#include "lapic.h"
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#include "irq.h"
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#if 0
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#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
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#else
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#define ioapic_debug(fmt, arg...)
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#endif
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static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq,
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bool line_status);
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static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
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unsigned long addr,
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unsigned long length)
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{
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unsigned long result = 0;
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switch (ioapic->ioregsel) {
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case IOAPIC_REG_VERSION:
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result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
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| (IOAPIC_VERSION_ID & 0xff));
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break;
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case IOAPIC_REG_APIC_ID:
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case IOAPIC_REG_ARB_ID:
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result = ((ioapic->id & 0xf) << 24);
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break;
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default:
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{
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u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
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u64 redir_content;
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if (redir_index < IOAPIC_NUM_PINS)
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redir_content =
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ioapic->redirtbl[redir_index].bits;
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else
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redir_content = ~0ULL;
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result = (ioapic->ioregsel & 0x1) ?
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(redir_content >> 32) & 0xffffffff :
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redir_content & 0xffffffff;
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break;
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}
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}
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return result;
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}
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static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic)
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{
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ioapic->rtc_status.pending_eoi = 0;
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bitmap_zero(ioapic->rtc_status.dest_map, KVM_MAX_VCPUS);
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}
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static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
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{
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bool new_val, old_val;
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struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
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union kvm_ioapic_redirect_entry *e;
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e = &ioapic->redirtbl[RTC_GSI];
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if (!kvm_apic_match_dest(vcpu, NULL, 0, e->fields.dest_id,
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e->fields.dest_mode))
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return;
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new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector);
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old_val = test_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map);
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if (new_val == old_val)
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return;
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if (new_val) {
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__set_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map);
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ioapic->rtc_status.pending_eoi++;
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} else {
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__clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map);
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ioapic->rtc_status.pending_eoi--;
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}
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WARN_ON(ioapic->rtc_status.pending_eoi < 0);
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}
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void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
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{
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struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
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spin_lock(&ioapic->lock);
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__rtc_irq_eoi_tracking_restore_one(vcpu);
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spin_unlock(&ioapic->lock);
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}
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static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic)
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{
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struct kvm_vcpu *vcpu;
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int i;
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if (RTC_GSI >= IOAPIC_NUM_PINS)
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return;
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rtc_irq_eoi_tracking_reset(ioapic);
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kvm_for_each_vcpu(i, vcpu, ioapic->kvm)
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__rtc_irq_eoi_tracking_restore_one(vcpu);
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}
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static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu)
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{
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if (test_and_clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map))
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--ioapic->rtc_status.pending_eoi;
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WARN_ON(ioapic->rtc_status.pending_eoi < 0);
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}
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static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic)
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{
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if (ioapic->rtc_status.pending_eoi > 0)
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return true; /* coalesced */
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return false;
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}
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static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx,
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bool line_status)
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{
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union kvm_ioapic_redirect_entry *pent;
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int injected = -1;
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pent = &ioapic->redirtbl[idx];
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if (!pent->fields.mask) {
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injected = ioapic_deliver(ioapic, idx, line_status);
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if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
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pent->fields.remote_irr = 1;
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}
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return injected;
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}
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static void update_handled_vectors(struct kvm_ioapic *ioapic)
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{
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DECLARE_BITMAP(handled_vectors, 256);
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int i;
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memset(handled_vectors, 0, sizeof(handled_vectors));
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for (i = 0; i < IOAPIC_NUM_PINS; ++i)
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__set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
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memcpy(ioapic->handled_vectors, handled_vectors,
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sizeof(handled_vectors));
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smp_wmb();
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}
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void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap,
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u32 *tmr)
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{
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struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
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union kvm_ioapic_redirect_entry *e;
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int index;
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spin_lock(&ioapic->lock);
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for (index = 0; index < IOAPIC_NUM_PINS; index++) {
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e = &ioapic->redirtbl[index];
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if (!e->fields.mask &&
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(e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
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kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC,
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index) || index == RTC_GSI)) {
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if (kvm_apic_match_dest(vcpu, NULL, 0,
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e->fields.dest_id, e->fields.dest_mode)) {
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__set_bit(e->fields.vector,
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(unsigned long *)eoi_exit_bitmap);
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if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG)
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__set_bit(e->fields.vector,
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(unsigned long *)tmr);
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}
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}
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}
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spin_unlock(&ioapic->lock);
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}
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#ifdef CONFIG_X86
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void kvm_vcpu_request_scan_ioapic(struct kvm *kvm)
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{
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struct kvm_ioapic *ioapic = kvm->arch.vioapic;
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if (!ioapic)
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return;
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kvm_make_scan_ioapic_request(kvm);
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}
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#else
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void kvm_vcpu_request_scan_ioapic(struct kvm *kvm)
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{
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return;
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}
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#endif
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static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
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{
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unsigned index;
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bool mask_before, mask_after;
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union kvm_ioapic_redirect_entry *e;
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switch (ioapic->ioregsel) {
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case IOAPIC_REG_VERSION:
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/* Writes are ignored. */
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break;
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case IOAPIC_REG_APIC_ID:
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ioapic->id = (val >> 24) & 0xf;
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break;
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case IOAPIC_REG_ARB_ID:
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break;
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default:
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index = (ioapic->ioregsel - 0x10) >> 1;
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ioapic_debug("change redir index %x val %x\n", index, val);
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if (index >= IOAPIC_NUM_PINS)
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return;
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e = &ioapic->redirtbl[index];
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mask_before = e->fields.mask;
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if (ioapic->ioregsel & 1) {
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e->bits &= 0xffffffff;
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e->bits |= (u64) val << 32;
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} else {
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e->bits &= ~0xffffffffULL;
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e->bits |= (u32) val;
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e->fields.remote_irr = 0;
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}
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update_handled_vectors(ioapic);
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mask_after = e->fields.mask;
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if (mask_before != mask_after)
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kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
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if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
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&& ioapic->irr & (1 << index))
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ioapic_service(ioapic, index, false);
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kvm_vcpu_request_scan_ioapic(ioapic->kvm);
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break;
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}
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}
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static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq, bool line_status)
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{
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union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
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struct kvm_lapic_irq irqe;
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int ret;
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ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
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"vector=%x trig_mode=%x\n",
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entry->fields.dest_id, entry->fields.dest_mode,
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entry->fields.delivery_mode, entry->fields.vector,
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entry->fields.trig_mode);
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irqe.dest_id = entry->fields.dest_id;
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irqe.vector = entry->fields.vector;
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irqe.dest_mode = entry->fields.dest_mode;
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irqe.trig_mode = entry->fields.trig_mode;
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irqe.delivery_mode = entry->fields.delivery_mode << 8;
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irqe.level = 1;
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irqe.shorthand = 0;
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if (irq == RTC_GSI && line_status) {
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BUG_ON(ioapic->rtc_status.pending_eoi != 0);
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ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe,
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ioapic->rtc_status.dest_map);
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ioapic->rtc_status.pending_eoi = ret;
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} else
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ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL);
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return ret;
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}
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
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int level, bool line_status)
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{
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u32 old_irr;
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u32 mask = 1 << irq;
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union kvm_ioapic_redirect_entry entry;
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int ret, irq_level;
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BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
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spin_lock(&ioapic->lock);
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old_irr = ioapic->irr;
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irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
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irq_source_id, level);
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entry = ioapic->redirtbl[irq];
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irq_level ^= entry.fields.polarity;
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if (!irq_level) {
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ioapic->irr &= ~mask;
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ret = 1;
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} else {
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int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
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if (irq == RTC_GSI && line_status &&
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rtc_irq_check_coalesced(ioapic)) {
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ret = 0; /* coalesced */
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goto out;
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}
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ioapic->irr |= mask;
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if ((edge && old_irr != ioapic->irr) ||
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(!edge && !entry.fields.remote_irr))
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ret = ioapic_service(ioapic, irq, line_status);
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else
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ret = 0; /* report coalesced interrupt */
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}
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out:
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trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
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spin_unlock(&ioapic->lock);
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return ret;
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}
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void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
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{
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int i;
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spin_lock(&ioapic->lock);
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for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
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__clear_bit(irq_source_id, &ioapic->irq_states[i]);
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spin_unlock(&ioapic->lock);
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}
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static void __kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu,
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struct kvm_ioapic *ioapic, int vector, int trigger_mode)
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{
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int i;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
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if (ent->fields.vector != vector)
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continue;
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if (i == RTC_GSI)
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rtc_irq_eoi(ioapic, vcpu);
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/*
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* We are dropping lock while calling ack notifiers because ack
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* notifier callbacks for assigned devices call into IOAPIC
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* recursively. Since remote_irr is cleared only after call
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* to notifiers if the same vector will be delivered while lock
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* is dropped it will be put into irr and will be delivered
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* after ack notifier returns.
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*/
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spin_unlock(&ioapic->lock);
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kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
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spin_lock(&ioapic->lock);
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if (trigger_mode != IOAPIC_LEVEL_TRIG)
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continue;
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ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
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ent->fields.remote_irr = 0;
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if (!ent->fields.mask && (ioapic->irr & (1 << i)))
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ioapic_service(ioapic, i, false);
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}
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}
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bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
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{
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struct kvm_ioapic *ioapic = kvm->arch.vioapic;
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smp_rmb();
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return test_bit(vector, ioapic->handled_vectors);
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}
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void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode)
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{
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struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
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spin_lock(&ioapic->lock);
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__kvm_ioapic_update_eoi(vcpu, ioapic, vector, trigger_mode);
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spin_unlock(&ioapic->lock);
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}
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static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
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{
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return container_of(dev, struct kvm_ioapic, dev);
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}
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static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
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{
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return ((addr >= ioapic->base_address &&
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(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
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}
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static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
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void *val)
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{
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struct kvm_ioapic *ioapic = to_ioapic(this);
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u32 result;
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if (!ioapic_in_range(ioapic, addr))
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return -EOPNOTSUPP;
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ioapic_debug("addr %lx\n", (unsigned long)addr);
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ASSERT(!(addr & 0xf)); /* check alignment */
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addr &= 0xff;
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spin_lock(&ioapic->lock);
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switch (addr) {
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case IOAPIC_REG_SELECT:
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result = ioapic->ioregsel;
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break;
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case IOAPIC_REG_WINDOW:
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result = ioapic_read_indirect(ioapic, addr, len);
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break;
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default:
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result = 0;
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break;
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}
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spin_unlock(&ioapic->lock);
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switch (len) {
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case 8:
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*(u64 *) val = result;
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break;
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case 1:
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case 2:
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case 4:
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memcpy(val, (char *)&result, len);
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break;
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default:
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printk(KERN_WARNING "ioapic: wrong length %d\n", len);
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}
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return 0;
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}
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static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
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const void *val)
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{
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struct kvm_ioapic *ioapic = to_ioapic(this);
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u32 data;
|
|
if (!ioapic_in_range(ioapic, addr))
|
|
return -EOPNOTSUPP;
|
|
|
|
ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
|
|
(void*)addr, len, val);
|
|
ASSERT(!(addr & 0xf)); /* check alignment */
|
|
|
|
switch (len) {
|
|
case 8:
|
|
case 4:
|
|
data = *(u32 *) val;
|
|
break;
|
|
case 2:
|
|
data = *(u16 *) val;
|
|
break;
|
|
case 1:
|
|
data = *(u8 *) val;
|
|
break;
|
|
default:
|
|
printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
|
|
return 0;
|
|
}
|
|
|
|
addr &= 0xff;
|
|
spin_lock(&ioapic->lock);
|
|
switch (addr) {
|
|
case IOAPIC_REG_SELECT:
|
|
ioapic->ioregsel = data & 0xFF; /* 8-bit register */
|
|
break;
|
|
|
|
case IOAPIC_REG_WINDOW:
|
|
ioapic_write_indirect(ioapic, data);
|
|
break;
|
|
#ifdef CONFIG_IA64
|
|
case IOAPIC_REG_EOI:
|
|
__kvm_ioapic_update_eoi(NULL, ioapic, data, IOAPIC_LEVEL_TRIG);
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
break;
|
|
}
|
|
spin_unlock(&ioapic->lock);
|
|
return 0;
|
|
}
|
|
|
|
void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < IOAPIC_NUM_PINS; i++)
|
|
ioapic->redirtbl[i].fields.mask = 1;
|
|
ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
|
|
ioapic->ioregsel = 0;
|
|
ioapic->irr = 0;
|
|
ioapic->id = 0;
|
|
rtc_irq_eoi_tracking_reset(ioapic);
|
|
update_handled_vectors(ioapic);
|
|
}
|
|
|
|
static const struct kvm_io_device_ops ioapic_mmio_ops = {
|
|
.read = ioapic_mmio_read,
|
|
.write = ioapic_mmio_write,
|
|
};
|
|
|
|
int kvm_ioapic_init(struct kvm *kvm)
|
|
{
|
|
struct kvm_ioapic *ioapic;
|
|
int ret;
|
|
|
|
ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
|
|
if (!ioapic)
|
|
return -ENOMEM;
|
|
spin_lock_init(&ioapic->lock);
|
|
kvm->arch.vioapic = ioapic;
|
|
kvm_ioapic_reset(ioapic);
|
|
kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
|
|
ioapic->kvm = kvm;
|
|
mutex_lock(&kvm->slots_lock);
|
|
ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
|
|
IOAPIC_MEM_LENGTH, &ioapic->dev);
|
|
mutex_unlock(&kvm->slots_lock);
|
|
if (ret < 0) {
|
|
kvm->arch.vioapic = NULL;
|
|
kfree(ioapic);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void kvm_ioapic_destroy(struct kvm *kvm)
|
|
{
|
|
struct kvm_ioapic *ioapic = kvm->arch.vioapic;
|
|
|
|
if (ioapic) {
|
|
kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
|
|
kvm->arch.vioapic = NULL;
|
|
kfree(ioapic);
|
|
}
|
|
}
|
|
|
|
int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
|
|
{
|
|
struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
|
|
if (!ioapic)
|
|
return -EINVAL;
|
|
|
|
spin_lock(&ioapic->lock);
|
|
memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
|
|
spin_unlock(&ioapic->lock);
|
|
return 0;
|
|
}
|
|
|
|
int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
|
|
{
|
|
struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
|
|
if (!ioapic)
|
|
return -EINVAL;
|
|
|
|
spin_lock(&ioapic->lock);
|
|
memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
|
|
update_handled_vectors(ioapic);
|
|
kvm_vcpu_request_scan_ioapic(kvm);
|
|
kvm_rtc_eoi_tracking_restore_all(ioapic);
|
|
spin_unlock(&ioapic->lock);
|
|
return 0;
|
|
}
|