mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 01:10:04 +00:00
4da9f33026
this has been brought into a shape which is maintainable and actually works. This final version was done by Sasha Levin who took it up after Intel dropped the ball. Sasha discovered that the SGX (sic!) offerings out there ship rogue kernel modules enabling FSGSBASE behind the kernels back which opens an instantanious unpriviledged root hole. The FSGSBASE instructions provide a considerable speedup of the context switch path and enable user space to write GSBASE without kernel interaction. This enablement requires careful handling of the exception entries which go through the paranoid entry path as they cannot longer rely on the assumption that user GSBASE is positive (as enforced via prctl() on non FSGSBASE enabled systemn). All other entries (syscalls, interrupts and exceptions) can still just utilize SWAPGS unconditionally when the entry comes from user space. Converting these entries to use FSGSBASE has no benefit as SWAPGS is only marginally slower than WRGSBASE and locating and retrieving the kernel GSBASE value is not a free operation either. The real benefit of RD/WRGSBASE is the avoidance of the MSR reads and writes. The changes come with appropriate selftests and have held up in field testing against the (sanitized) Graphene-SGX driver. -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAl8pGnoTHHRnbHhAbGlu dXRyb25peC5kZQAKCRCmGPVMDXSYoTYJD/9873GkwvGcc/Vq/dJH1szGTgFftPyZ c/Y9gzx7EGBPLo25BS820L+ZlynzXHDxExKfCEaD10TZfe5XIc1vYNR0J74M2NmK IBgEDstJeW93ai+rHCFRXIevhpzU4GgGYJ1MeeOgbVMN3aGU1g6HfzMvtF0fPn8Y n6fsLZa43wgnoTdjwjjikpDTrzoZbaL1mbODBzBVPAaTbim7IKKTge6r/iCKrOjz Uixvm3g9lVzx52zidJ9kWa8esmbOM1j0EPe7/hy3qH9DFo87KxEzjHNH3T6gY5t6 NJhRAIfY+YyTHpPCUCshj6IkRudE6w/qjEAmKP9kWZxoJrvPCTWOhCzelwsFS9b9 gxEYfsnaKhsfNhB6fi0PtWlMzPINmEA7SuPza33u5WtQUK7s1iNlgHfvMbjstbwg MSETn4SG2/ZyzUrSC06lVwV8kh0RgM3cENc/jpFfIHD0vKGI3qfka/1RY94kcOCG AeJd0YRSU2RqL7lmxhHyG8tdb8eexns41IzbPCLXX2sF00eKNkVvMRYT2mKfKLFF q8v1x7yuwmODdXfFR6NdCkGm9IU7wtL6wuQ8Nhu9UraFmcXo6X6FLJC18FqcvSb9 jvcRP4XY/8pNjjf44JB8yWfah0xGQsaMIKQGP4yLv4j6Xk1xAQKH1MqcC7l1D2HN 5Z24GibFqSK/vA== =QaAN -----END PGP SIGNATURE----- Merge tag 'x86-fsgsbase-2020-08-04' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fsgsbase from Thomas Gleixner: "Support for FSGSBASE. Almost 5 years after the first RFC to support it, this has been brought into a shape which is maintainable and actually works. This final version was done by Sasha Levin who took it up after Intel dropped the ball. Sasha discovered that the SGX (sic!) offerings out there ship rogue kernel modules enabling FSGSBASE behind the kernels back which opens an instantanious unpriviledged root hole. The FSGSBASE instructions provide a considerable speedup of the context switch path and enable user space to write GSBASE without kernel interaction. This enablement requires careful handling of the exception entries which go through the paranoid entry path as they can no longer rely on the assumption that user GSBASE is positive (as enforced via prctl() on non FSGSBASE enabled systemn). All other entries (syscalls, interrupts and exceptions) can still just utilize SWAPGS unconditionally when the entry comes from user space. Converting these entries to use FSGSBASE has no benefit as SWAPGS is only marginally slower than WRGSBASE and locating and retrieving the kernel GSBASE value is not a free operation either. The real benefit of RD/WRGSBASE is the avoidance of the MSR reads and writes. The changes come with appropriate selftests and have held up in field testing against the (sanitized) Graphene-SGX driver" * tag 'x86-fsgsbase-2020-08-04' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits) x86/fsgsbase: Fix Xen PV support x86/ptrace: Fix 32-bit PTRACE_SETREGS vs fsbase and gsbase selftests/x86/fsgsbase: Add a missing memory constraint selftests/x86/fsgsbase: Fix a comment in the ptrace_write_gsbase test selftests/x86: Add a syscall_arg_fault_64 test for negative GSBASE selftests/x86/fsgsbase: Test ptracer-induced GS base write with FSGSBASE selftests/x86/fsgsbase: Test GS selector on ptracer-induced GS base write Documentation/x86/64: Add documentation for GS/FS addressing mode x86/elf: Enumerate kernel FSGSBASE capability in AT_HWCAP2 x86/cpu: Enable FSGSBASE on 64bit by default and add a chicken bit x86/entry/64: Handle FSGSBASE enabled paranoid entry/exit x86/entry/64: Introduce the FIND_PERCPU_BASE macro x86/entry/64: Switch CR3 before SWAPGS in paranoid entry x86/speculation/swapgs: Check FSGSBASE in enabling SWAPGS mitigation x86/process/64: Use FSGSBASE instructions on thread copy and ptrace x86/process/64: Use FSBSBASE in switch_to() if available x86/process/64: Make save_fsgs_for_kvm() ready for FSGSBASE x86/fsgsbase/64: Enable FSGSBASE instructions in helper functions x86/fsgsbase/64: Add intrinsics for FSGSBASE instructions x86/cpu: Add 'unsafe_fsgsbase' to enable CR4.FSGSBASE ...
163 lines
2.3 KiB
C
163 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Generate .byte code for some instructions not supported by old
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* binutils.
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*/
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#ifndef X86_ASM_INST_H
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#define X86_ASM_INST_H
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#ifdef __ASSEMBLY__
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#define REG_NUM_INVALID 100
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#define REG_TYPE_R32 0
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#define REG_TYPE_R64 1
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#define REG_TYPE_INVALID 100
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.macro R32_NUM opd r32
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\opd = REG_NUM_INVALID
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.ifc \r32,%eax
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\opd = 0
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.endif
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.ifc \r32,%ecx
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\opd = 1
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.endif
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.ifc \r32,%edx
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\opd = 2
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.endif
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.ifc \r32,%ebx
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\opd = 3
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.endif
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.ifc \r32,%esp
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\opd = 4
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.endif
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.ifc \r32,%ebp
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\opd = 5
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.endif
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.ifc \r32,%esi
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\opd = 6
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.endif
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.ifc \r32,%edi
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\opd = 7
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.endif
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#ifdef CONFIG_X86_64
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.ifc \r32,%r8d
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\opd = 8
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.endif
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.ifc \r32,%r9d
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\opd = 9
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.endif
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.ifc \r32,%r10d
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\opd = 10
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.endif
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.ifc \r32,%r11d
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\opd = 11
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.endif
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.ifc \r32,%r12d
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\opd = 12
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.endif
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.ifc \r32,%r13d
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\opd = 13
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.endif
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.ifc \r32,%r14d
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\opd = 14
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.endif
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.ifc \r32,%r15d
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\opd = 15
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.endif
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#endif
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.endm
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.macro R64_NUM opd r64
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\opd = REG_NUM_INVALID
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#ifdef CONFIG_X86_64
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.ifc \r64,%rax
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\opd = 0
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.endif
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.ifc \r64,%rcx
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\opd = 1
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.endif
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.ifc \r64,%rdx
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\opd = 2
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.endif
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.ifc \r64,%rbx
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\opd = 3
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.endif
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.ifc \r64,%rsp
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\opd = 4
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.endif
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.ifc \r64,%rbp
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\opd = 5
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.endif
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.ifc \r64,%rsi
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\opd = 6
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.endif
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.ifc \r64,%rdi
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\opd = 7
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.endif
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.ifc \r64,%r8
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\opd = 8
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.endif
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.ifc \r64,%r9
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\opd = 9
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.endif
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.ifc \r64,%r10
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\opd = 10
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.endif
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.ifc \r64,%r11
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\opd = 11
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.endif
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.ifc \r64,%r12
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\opd = 12
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.endif
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.ifc \r64,%r13
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\opd = 13
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.endif
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.ifc \r64,%r14
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\opd = 14
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.endif
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.ifc \r64,%r15
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\opd = 15
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.endif
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#endif
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.endm
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.macro REG_TYPE type reg
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R32_NUM reg_type_r32 \reg
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R64_NUM reg_type_r64 \reg
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.if reg_type_r64 <> REG_NUM_INVALID
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\type = REG_TYPE_R64
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.elseif reg_type_r32 <> REG_NUM_INVALID
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\type = REG_TYPE_R32
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.else
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\type = REG_TYPE_INVALID
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.endif
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.endm
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.macro PFX_REX opd1 opd2 W=0
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.if ((\opd1 | \opd2) & 8) || \W
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.byte 0x40 | ((\opd1 & 8) >> 3) | ((\opd2 & 8) >> 1) | (\W << 3)
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.endif
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.endm
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.macro MODRM mod opd1 opd2
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.byte \mod | (\opd1 & 7) | ((\opd2 & 7) << 3)
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.endm
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.macro RDPID opd
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REG_TYPE rdpid_opd_type \opd
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.if rdpid_opd_type == REG_TYPE_R64
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R64_NUM rdpid_opd \opd
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.else
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R32_NUM rdpid_opd \opd
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.endif
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.byte 0xf3
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.if rdpid_opd > 7
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PFX_REX rdpid_opd 0
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.endif
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.byte 0x0f, 0xc7
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MODRM 0xc0 rdpid_opd 0x7
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.endm
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#endif
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#endif
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