mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-11 11:09:13 +00:00
da9803dfd3
called SEV by also encrypting the guest register state, making the
registers inaccessible to the hypervisor by en-/decrypting them on world
switches. Thus, it adds additional protection to Linux guests against
exfiltration, control flow and rollback attacks.
With SEV-ES, the guest is in full control of what registers the
hypervisor can access. This is provided by a guest-host exchange
mechanism based on a new exception vector called VMM Communication
Exception (#VC), a new instruction called VMGEXIT and a shared
Guest-Host Communication Block which is a decrypted page shared between
the guest and the hypervisor.
Intercepts to the hypervisor become #VC exceptions in an SEV-ES guest so
in order for that exception mechanism to work, the early x86 init code
needed to be made able to handle exceptions, which, in itself, brings
a bunch of very nice cleanups and improvements to the early boot code
like an early page fault handler, allowing for on-demand building of the
identity mapping. With that, !KASLR configurations do not use the EFI
page table anymore but switch to a kernel-controlled one.
The main part of this series adds the support for that new exchange
mechanism. The goal has been to keep this as much as possibly
separate from the core x86 code by concentrating the machinery in two
SEV-ES-specific files:
arch/x86/kernel/sev-es-shared.c
arch/x86/kernel/sev-es.c
Other interaction with core x86 code has been kept at minimum and behind
static keys to minimize the performance impact on !SEV-ES setups.
Work by Joerg Roedel and Thomas Lendacky and others.
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Merge tag 'x86_seves_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 SEV-ES support from Borislav Petkov:
"SEV-ES enhances the current guest memory encryption support called SEV
by also encrypting the guest register state, making the registers
inaccessible to the hypervisor by en-/decrypting them on world
switches. Thus, it adds additional protection to Linux guests against
exfiltration, control flow and rollback attacks.
With SEV-ES, the guest is in full control of what registers the
hypervisor can access. This is provided by a guest-host exchange
mechanism based on a new exception vector called VMM Communication
Exception (#VC), a new instruction called VMGEXIT and a shared
Guest-Host Communication Block which is a decrypted page shared
between the guest and the hypervisor.
Intercepts to the hypervisor become #VC exceptions in an SEV-ES guest
so in order for that exception mechanism to work, the early x86 init
code needed to be made able to handle exceptions, which, in itself,
brings a bunch of very nice cleanups and improvements to the early
boot code like an early page fault handler, allowing for on-demand
building of the identity mapping. With that, !KASLR configurations do
not use the EFI page table anymore but switch to a kernel-controlled
one.
The main part of this series adds the support for that new exchange
mechanism. The goal has been to keep this as much as possibly separate
from the core x86 code by concentrating the machinery in two
SEV-ES-specific files:
arch/x86/kernel/sev-es-shared.c
arch/x86/kernel/sev-es.c
Other interaction with core x86 code has been kept at minimum and
behind static keys to minimize the performance impact on !SEV-ES
setups.
Work by Joerg Roedel and Thomas Lendacky and others"
* tag 'x86_seves_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (73 commits)
x86/sev-es: Use GHCB accessor for setting the MMIO scratch buffer
x86/sev-es: Check required CPU features for SEV-ES
x86/efi: Add GHCB mappings when SEV-ES is active
x86/sev-es: Handle NMI State
x86/sev-es: Support CPU offline/online
x86/head/64: Don't call verify_cpu() on starting APs
x86/smpboot: Load TSS and getcpu GDT entry before loading IDT
x86/realmode: Setup AP jump table
x86/realmode: Add SEV-ES specific trampoline entry point
x86/vmware: Add VMware-specific handling for VMMCALL under SEV-ES
x86/kvm: Add KVM-specific VMMCALL handling under SEV-ES
x86/paravirt: Allow hypervisor-specific VMMCALL handling under SEV-ES
x86/sev-es: Handle #DB Events
x86/sev-es: Handle #AC Events
x86/sev-es: Handle VMMCALL Events
x86/sev-es: Handle MWAIT/MWAITX Events
x86/sev-es: Handle MONITOR/MONITORX Events
x86/sev-es: Handle INVD Events
x86/sev-es: Handle RDPMC Events
x86/sev-es: Handle RDTSC(P) Events
...
388 lines
11 KiB
C
388 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_SEGMENT_H
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#define _ASM_X86_SEGMENT_H
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#include <linux/const.h>
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#include <asm/alternative.h>
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/*
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* Constructor for a conventional segment GDT (or LDT) entry.
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* This is a macro so it can be used in initializers.
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*/
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#define GDT_ENTRY(flags, base, limit) \
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((((base) & _AC(0xff000000,ULL)) << (56-24)) | \
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(((flags) & _AC(0x0000f0ff,ULL)) << 40) | \
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(((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \
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(((base) & _AC(0x00ffffff,ULL)) << 16) | \
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(((limit) & _AC(0x0000ffff,ULL))))
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/* Simple and small GDT entries for booting only: */
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#define GDT_ENTRY_BOOT_CS 2
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#define GDT_ENTRY_BOOT_DS 3
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#define GDT_ENTRY_BOOT_TSS 4
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#define __BOOT_CS (GDT_ENTRY_BOOT_CS*8)
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#define __BOOT_DS (GDT_ENTRY_BOOT_DS*8)
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#define __BOOT_TSS (GDT_ENTRY_BOOT_TSS*8)
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/*
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* Bottom two bits of selector give the ring
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* privilege level
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*/
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#define SEGMENT_RPL_MASK 0x3
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/*
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* When running on Xen PV, the actual privilege level of the kernel is 1,
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* not 0. Testing the Requested Privilege Level in a segment selector to
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* determine whether the context is user mode or kernel mode with
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* SEGMENT_RPL_MASK is wrong because the PV kernel's privilege level
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* matches the 0x3 mask.
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*
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* Testing with USER_SEGMENT_RPL_MASK is valid for both native and Xen PV
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* kernels because privilege level 2 is never used.
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*/
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#define USER_SEGMENT_RPL_MASK 0x2
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/* User mode is privilege level 3: */
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#define USER_RPL 0x3
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/* Bit 2 is Table Indicator (TI): selects between LDT or GDT */
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#define SEGMENT_TI_MASK 0x4
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/* LDT segment has TI set ... */
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#define SEGMENT_LDT 0x4
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/* ... GDT has it cleared */
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#define SEGMENT_GDT 0x0
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#define GDT_ENTRY_INVALID_SEG 0
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#ifdef CONFIG_X86_32
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/*
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* The layout of the per-CPU GDT under Linux:
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*
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* 0 - null <=== cacheline #1
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* 1 - reserved
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* 2 - reserved
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* 3 - reserved
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*
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* 4 - unused <=== cacheline #2
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* 5 - unused
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*
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* ------- start of TLS (Thread-Local Storage) segments:
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*
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* 6 - TLS segment #1 [ glibc's TLS segment ]
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* 7 - TLS segment #2 [ Wine's %fs Win32 segment ]
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* 8 - TLS segment #3 <=== cacheline #3
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* 9 - reserved
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* 10 - reserved
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* 11 - reserved
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*
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* ------- start of kernel segments:
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*
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* 12 - kernel code segment <=== cacheline #4
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* 13 - kernel data segment
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* 14 - default user CS
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* 15 - default user DS
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* 16 - TSS <=== cacheline #5
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* 17 - LDT
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* 18 - PNPBIOS support (16->32 gate)
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* 19 - PNPBIOS support
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* 20 - PNPBIOS support <=== cacheline #6
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* 21 - PNPBIOS support
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* 22 - PNPBIOS support
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* 23 - APM BIOS support
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* 24 - APM BIOS support <=== cacheline #7
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* 25 - APM BIOS support
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*
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* 26 - ESPFIX small SS
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* 27 - per-cpu [ offset to per-cpu data area ]
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* 28 - stack_canary-20 [ for stack protector ] <=== cacheline #8
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* 29 - unused
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* 30 - unused
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* 31 - TSS for double fault handler
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*/
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#define GDT_ENTRY_TLS_MIN 6
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#define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
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#define GDT_ENTRY_KERNEL_CS 12
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#define GDT_ENTRY_KERNEL_DS 13
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#define GDT_ENTRY_DEFAULT_USER_CS 14
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#define GDT_ENTRY_DEFAULT_USER_DS 15
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#define GDT_ENTRY_TSS 16
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#define GDT_ENTRY_LDT 17
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#define GDT_ENTRY_PNPBIOS_CS32 18
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#define GDT_ENTRY_PNPBIOS_CS16 19
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#define GDT_ENTRY_PNPBIOS_DS 20
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#define GDT_ENTRY_PNPBIOS_TS1 21
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#define GDT_ENTRY_PNPBIOS_TS2 22
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#define GDT_ENTRY_APMBIOS_BASE 23
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#define GDT_ENTRY_ESPFIX_SS 26
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#define GDT_ENTRY_PERCPU 27
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#define GDT_ENTRY_STACK_CANARY 28
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#define GDT_ENTRY_DOUBLEFAULT_TSS 31
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/*
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* Number of entries in the GDT table:
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*/
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#define GDT_ENTRIES 32
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/*
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* Segment selector values corresponding to the above entries:
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*/
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#define __KERNEL_CS (GDT_ENTRY_KERNEL_CS*8)
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#define __KERNEL_DS (GDT_ENTRY_KERNEL_DS*8)
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#define __USER_DS (GDT_ENTRY_DEFAULT_USER_DS*8 + 3)
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#define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS*8 + 3)
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#define __ESPFIX_SS (GDT_ENTRY_ESPFIX_SS*8)
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/* segment for calling fn: */
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#define PNP_CS32 (GDT_ENTRY_PNPBIOS_CS32*8)
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/* code segment for BIOS: */
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#define PNP_CS16 (GDT_ENTRY_PNPBIOS_CS16*8)
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/* "Is this PNP code selector (PNP_CS32 or PNP_CS16)?" */
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#define SEGMENT_IS_PNP_CODE(x) (((x) & 0xf4) == PNP_CS32)
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/* data segment for BIOS: */
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#define PNP_DS (GDT_ENTRY_PNPBIOS_DS*8)
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/* transfer data segment: */
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#define PNP_TS1 (GDT_ENTRY_PNPBIOS_TS1*8)
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/* another data segment: */
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#define PNP_TS2 (GDT_ENTRY_PNPBIOS_TS2*8)
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#ifdef CONFIG_SMP
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# define __KERNEL_PERCPU (GDT_ENTRY_PERCPU*8)
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#else
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# define __KERNEL_PERCPU 0
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#endif
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#ifdef CONFIG_STACKPROTECTOR
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# define __KERNEL_STACK_CANARY (GDT_ENTRY_STACK_CANARY*8)
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#else
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# define __KERNEL_STACK_CANARY 0
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#endif
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#else /* 64-bit: */
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#include <asm/cache.h>
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#define GDT_ENTRY_KERNEL32_CS 1
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#define GDT_ENTRY_KERNEL_CS 2
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#define GDT_ENTRY_KERNEL_DS 3
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/*
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* We cannot use the same code segment descriptor for user and kernel mode,
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* not even in long flat mode, because of different DPL.
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*
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* GDT layout to get 64-bit SYSCALL/SYSRET support right. SYSRET hardcodes
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* selectors:
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*
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* if returning to 32-bit userspace: cs = STAR.SYSRET_CS,
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* if returning to 64-bit userspace: cs = STAR.SYSRET_CS+16,
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*
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* ss = STAR.SYSRET_CS+8 (in either case)
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*
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* thus USER_DS should be between 32-bit and 64-bit code selectors:
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*/
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#define GDT_ENTRY_DEFAULT_USER32_CS 4
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#define GDT_ENTRY_DEFAULT_USER_DS 5
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#define GDT_ENTRY_DEFAULT_USER_CS 6
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/* Needs two entries */
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#define GDT_ENTRY_TSS 8
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/* Needs two entries */
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#define GDT_ENTRY_LDT 10
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#define GDT_ENTRY_TLS_MIN 12
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#define GDT_ENTRY_TLS_MAX 14
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#define GDT_ENTRY_CPUNODE 15
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/*
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* Number of entries in the GDT table:
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*/
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#define GDT_ENTRIES 16
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/*
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* Segment selector values corresponding to the above entries:
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*
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* Note, selectors also need to have a correct RPL,
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* expressed with the +3 value for user-space selectors:
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*/
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#define __KERNEL32_CS (GDT_ENTRY_KERNEL32_CS*8)
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#define __KERNEL_CS (GDT_ENTRY_KERNEL_CS*8)
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#define __KERNEL_DS (GDT_ENTRY_KERNEL_DS*8)
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#define __USER32_CS (GDT_ENTRY_DEFAULT_USER32_CS*8 + 3)
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#define __USER_DS (GDT_ENTRY_DEFAULT_USER_DS*8 + 3)
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#define __USER32_DS __USER_DS
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#define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS*8 + 3)
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#define __CPUNODE_SEG (GDT_ENTRY_CPUNODE*8 + 3)
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#endif
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#define IDT_ENTRIES 256
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#define NUM_EXCEPTION_VECTORS 32
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/* Bitmask of exception vectors which push an error code on the stack: */
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#define EXCEPTION_ERRCODE_MASK 0x20027d00
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#define GDT_SIZE (GDT_ENTRIES*8)
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#define GDT_ENTRY_TLS_ENTRIES 3
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#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES* 8)
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#ifdef CONFIG_X86_64
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/* Bit size and mask of CPU number stored in the per CPU data (and TSC_AUX) */
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#define VDSO_CPUNODE_BITS 12
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#define VDSO_CPUNODE_MASK 0xfff
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#ifndef __ASSEMBLY__
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/* Helper functions to store/load CPU and node numbers */
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static inline unsigned long vdso_encode_cpunode(int cpu, unsigned long node)
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{
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return (node << VDSO_CPUNODE_BITS) | cpu;
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}
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static inline void vdso_read_cpunode(unsigned *cpu, unsigned *node)
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{
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unsigned int p;
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/*
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* Load CPU and node number from the GDT. LSL is faster than RDTSCP
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* and works on all CPUs. This is volatile so that it orders
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* correctly with respect to barrier() and to keep GCC from cleverly
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* hoisting it out of the calling function.
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*
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* If RDPID is available, use it.
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*/
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alternative_io ("lsl %[seg],%[p]",
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".byte 0xf3,0x0f,0xc7,0xf8", /* RDPID %eax/rax */
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X86_FEATURE_RDPID,
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[p] "=a" (p), [seg] "r" (__CPUNODE_SEG));
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if (cpu)
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*cpu = (p & VDSO_CPUNODE_MASK);
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if (node)
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*node = (p >> VDSO_CPUNODE_BITS);
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* CONFIG_X86_64 */
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#ifdef __KERNEL__
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/*
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* early_idt_handler_array is an array of entry points referenced in the
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* early IDT. For simplicity, it's a real array with one entry point
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* every nine bytes. That leaves room for an optional 'push $0' if the
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* vector has no error code (two bytes), a 'push $vector_number' (two
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* bytes), and a jump to the common entry code (up to five bytes).
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*/
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#define EARLY_IDT_HANDLER_SIZE 9
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/*
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* xen_early_idt_handler_array is for Xen pv guests: for each entry in
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* early_idt_handler_array it contains a prequel in the form of
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* pop %rcx; pop %r11; jmp early_idt_handler_array[i]; summing up to
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* max 8 bytes.
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*/
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#define XEN_EARLY_IDT_HANDLER_SIZE 8
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#ifndef __ASSEMBLY__
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extern const char early_idt_handler_array[NUM_EXCEPTION_VECTORS][EARLY_IDT_HANDLER_SIZE];
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extern void early_ignore_irq(void);
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#ifdef CONFIG_XEN_PV
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extern const char xen_early_idt_handler_array[NUM_EXCEPTION_VECTORS][XEN_EARLY_IDT_HANDLER_SIZE];
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#endif
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/*
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* Load a segment. Fall back on loading the zero segment if something goes
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* wrong. This variant assumes that loading zero fully clears the segment.
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* This is always the case on Intel CPUs and, even on 64-bit AMD CPUs, any
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* failure to fully clear the cached descriptor is only observable for
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* FS and GS.
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*/
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#define __loadsegment_simple(seg, value) \
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do { \
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unsigned short __val = (value); \
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\
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asm volatile(" \n" \
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"1: movl %k0,%%" #seg " \n" \
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\
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".section .fixup,\"ax\" \n" \
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"2: xorl %k0,%k0 \n" \
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" jmp 1b \n" \
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".previous \n" \
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\
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_ASM_EXTABLE(1b, 2b) \
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\
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: "+r" (__val) : : "memory"); \
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} while (0)
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#define __loadsegment_ss(value) __loadsegment_simple(ss, (value))
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#define __loadsegment_ds(value) __loadsegment_simple(ds, (value))
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#define __loadsegment_es(value) __loadsegment_simple(es, (value))
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#ifdef CONFIG_X86_32
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/*
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* On 32-bit systems, the hidden parts of FS and GS are unobservable if
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* the selector is NULL, so there's no funny business here.
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*/
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#define __loadsegment_fs(value) __loadsegment_simple(fs, (value))
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#define __loadsegment_gs(value) __loadsegment_simple(gs, (value))
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#else
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static inline void __loadsegment_fs(unsigned short value)
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{
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asm volatile(" \n"
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"1: movw %0, %%fs \n"
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"2: \n"
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_ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_clear_fs)
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: : "rm" (value) : "memory");
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}
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/* __loadsegment_gs is intentionally undefined. Use load_gs_index instead. */
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#endif
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#define loadsegment(seg, value) __loadsegment_ ## seg (value)
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/*
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* Save a segment register away:
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*/
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#define savesegment(seg, value) \
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asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
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/*
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* x86-32 user GS accessors:
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*/
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#ifdef CONFIG_X86_32
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# ifdef CONFIG_X86_32_LAZY_GS
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# define get_user_gs(regs) (u16)({ unsigned long v; savesegment(gs, v); v; })
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# define set_user_gs(regs, v) loadsegment(gs, (unsigned long)(v))
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# define task_user_gs(tsk) ((tsk)->thread.gs)
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# define lazy_save_gs(v) savesegment(gs, (v))
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# define lazy_load_gs(v) loadsegment(gs, (v))
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# else /* X86_32_LAZY_GS */
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# define get_user_gs(regs) (u16)((regs)->gs)
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# define set_user_gs(regs, v) do { (regs)->gs = (v); } while (0)
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# define task_user_gs(tsk) (task_pt_regs(tsk)->gs)
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# define lazy_save_gs(v) do { } while (0)
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# define lazy_load_gs(v) do { } while (0)
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# endif /* X86_32_LAZY_GS */
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#endif /* X86_32 */
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_SEGMENT_H */
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