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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 or at your option any later version you should have received a copy of the gnu general public license for example usr src linux copying if not write to the free software foundation inc 675 mass ave cambridge ma 02139 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 20 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190520170858.552543146@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
488 lines
9.9 KiB
C
488 lines
9.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _ASM_X86_XOR_H
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#define _ASM_X86_XOR_H
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/*
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* Optimized RAID-5 checksumming functions for SSE.
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*/
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/*
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* Cache avoiding checksumming functions utilizing KNI instructions
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* Copyright (C) 1999 Zach Brown (with obvious credit due Ingo)
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*/
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/*
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* Based on
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* High-speed RAID5 checksumming functions utilizing SSE instructions.
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* Copyright (C) 1998 Ingo Molnar.
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*/
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/*
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* x86-64 changes / gcc fixes from Andi Kleen.
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* Copyright 2002 Andi Kleen, SuSE Labs.
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*
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* This hasn't been optimized for the hammer yet, but there are likely
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* no advantages to be gotten from x86-64 here anyways.
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*/
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#include <asm/fpu/api.h>
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#ifdef CONFIG_X86_32
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/* reduce register pressure */
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# define XOR_CONSTANT_CONSTRAINT "i"
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#else
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# define XOR_CONSTANT_CONSTRAINT "re"
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#endif
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#define OFFS(x) "16*("#x")"
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#define PF_OFFS(x) "256+16*("#x")"
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#define PF0(x) " prefetchnta "PF_OFFS(x)"(%[p1]) ;\n"
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#define LD(x, y) " movaps "OFFS(x)"(%[p1]), %%xmm"#y" ;\n"
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#define ST(x, y) " movaps %%xmm"#y", "OFFS(x)"(%[p1]) ;\n"
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#define PF1(x) " prefetchnta "PF_OFFS(x)"(%[p2]) ;\n"
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#define PF2(x) " prefetchnta "PF_OFFS(x)"(%[p3]) ;\n"
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#define PF3(x) " prefetchnta "PF_OFFS(x)"(%[p4]) ;\n"
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#define PF4(x) " prefetchnta "PF_OFFS(x)"(%[p5]) ;\n"
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#define XO1(x, y) " xorps "OFFS(x)"(%[p2]), %%xmm"#y" ;\n"
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#define XO2(x, y) " xorps "OFFS(x)"(%[p3]), %%xmm"#y" ;\n"
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#define XO3(x, y) " xorps "OFFS(x)"(%[p4]), %%xmm"#y" ;\n"
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#define XO4(x, y) " xorps "OFFS(x)"(%[p5]), %%xmm"#y" ;\n"
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#define NOP(x)
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#define BLK64(pf, op, i) \
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pf(i) \
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op(i, 0) \
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op(i + 1, 1) \
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op(i + 2, 2) \
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op(i + 3, 3)
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static void
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xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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LD(i, 0) \
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LD(i + 1, 1) \
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PF1(i) \
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PF1(i + 2) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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PF0(i + 4) \
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PF0(i + 6) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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ST(i, 0) \
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ST(i + 1, 1) \
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ST(i + 2, 2) \
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ST(i + 3, 3) \
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PF0(0)
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PF0(2)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines),
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[p1] "+r" (p1), [p2] "+r" (p2)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_sse_2_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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BLK64(PF0, LD, i) \
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BLK64(PF1, XO1, i) \
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BLK64(NOP, ST, i) \
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines),
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[p1] "+r" (p1), [p2] "+r" (p2)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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PF1(i) \
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PF1(i + 2) \
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LD(i, 0) \
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LD(i + 1, 1) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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PF2(i) \
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PF2(i + 2) \
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PF0(i + 4) \
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PF0(i + 6) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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XO2(i, 0) \
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XO2(i + 1, 1) \
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XO2(i + 2, 2) \
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XO2(i + 3, 3) \
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ST(i, 0) \
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ST(i + 1, 1) \
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ST(i + 2, 2) \
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ST(i + 3, 3) \
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PF0(0)
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PF0(2)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" add %[inc], %[p3] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines),
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[p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_sse_3_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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BLK64(PF0, LD, i) \
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BLK64(PF1, XO1, i) \
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BLK64(PF2, XO2, i) \
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BLK64(NOP, ST, i) \
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" add %[inc], %[p3] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines),
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[p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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PF1(i) \
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PF1(i + 2) \
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LD(i, 0) \
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LD(i + 1, 1) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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PF2(i) \
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PF2(i + 2) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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PF3(i) \
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PF3(i + 2) \
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PF0(i + 4) \
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PF0(i + 6) \
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XO2(i, 0) \
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XO2(i + 1, 1) \
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XO2(i + 2, 2) \
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XO2(i + 3, 3) \
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XO3(i, 0) \
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XO3(i + 1, 1) \
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XO3(i + 2, 2) \
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XO3(i + 3, 3) \
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ST(i, 0) \
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ST(i + 1, 1) \
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ST(i + 2, 2) \
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ST(i + 3, 3) \
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PF0(0)
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PF0(2)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" add %[inc], %[p3] ;\n"
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" add %[inc], %[p4] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines), [p1] "+r" (p1),
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[p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_sse_4_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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BLK64(PF0, LD, i) \
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BLK64(PF1, XO1, i) \
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BLK64(PF2, XO2, i) \
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BLK64(PF3, XO3, i) \
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BLK64(NOP, ST, i) \
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" add %[inc], %[p3] ;\n"
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" add %[inc], %[p4] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines), [p1] "+r" (p1),
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[p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4, unsigned long *p5)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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PF1(i) \
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PF1(i + 2) \
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LD(i, 0) \
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LD(i + 1, 1) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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PF2(i) \
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PF2(i + 2) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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PF3(i) \
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PF3(i + 2) \
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XO2(i, 0) \
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XO2(i + 1, 1) \
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XO2(i + 2, 2) \
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XO2(i + 3, 3) \
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PF4(i) \
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PF4(i + 2) \
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PF0(i + 4) \
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PF0(i + 6) \
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XO3(i, 0) \
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XO3(i + 1, 1) \
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XO3(i + 2, 2) \
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XO3(i + 3, 3) \
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XO4(i, 0) \
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XO4(i + 1, 1) \
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XO4(i + 2, 2) \
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XO4(i + 3, 3) \
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ST(i, 0) \
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ST(i + 1, 1) \
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ST(i + 2, 2) \
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ST(i + 3, 3) \
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PF0(0)
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PF0(2)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" add %[inc], %[p3] ;\n"
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" add %[inc], %[p4] ;\n"
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" add %[inc], %[p5] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines), [p1] "+r" (p1), [p2] "+r" (p2),
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[p3] "+r" (p3), [p4] "+r" (p4), [p5] "+r" (p5)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_sse_5_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4, unsigned long *p5)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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BLK64(PF0, LD, i) \
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BLK64(PF1, XO1, i) \
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BLK64(PF2, XO2, i) \
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BLK64(PF3, XO3, i) \
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BLK64(PF4, XO4, i) \
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BLK64(NOP, ST, i) \
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" add %[inc], %[p3] ;\n"
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" add %[inc], %[p4] ;\n"
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" add %[inc], %[p5] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines), [p1] "+r" (p1), [p2] "+r" (p2),
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[p3] "+r" (p3), [p4] "+r" (p4), [p5] "+r" (p5)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static struct xor_block_template xor_block_sse_pf64 = {
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.name = "prefetch64-sse",
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.do_2 = xor_sse_2_pf64,
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.do_3 = xor_sse_3_pf64,
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.do_4 = xor_sse_4_pf64,
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.do_5 = xor_sse_5_pf64,
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};
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#undef LD
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#undef XO1
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#undef XO2
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#undef XO3
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#undef XO4
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#undef ST
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#undef NOP
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#undef BLK64
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#undef BLOCK
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#undef XOR_CONSTANT_CONSTRAINT
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#ifdef CONFIG_X86_32
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# include <asm/xor_32.h>
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#else
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# include <asm/xor_64.h>
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#endif
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#define XOR_SELECT_TEMPLATE(FASTEST) \
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AVX_SELECT(FASTEST)
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#endif /* _ASM_X86_XOR_H */
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