136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#ifndef PVR_FW_INFO_H
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#define PVR_FW_INFO_H
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#include <linux/bits.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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/*
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* Firmware binary block unit in bytes.
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* Raw data stored in FW binary will be aligned to this size.
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*/
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#define FW_BLOCK_SIZE SZ_4K
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/* Maximum number of entries in firmware layout table. */
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#define PVR_FW_INFO_MAX_NUM_ENTRIES 8
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enum pvr_fw_section_id {
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META_CODE = 0,
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META_PRIVATE_DATA,
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META_COREMEM_CODE,
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META_COREMEM_DATA,
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MIPS_CODE,
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MIPS_EXCEPTIONS_CODE,
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MIPS_BOOT_CODE,
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MIPS_PRIVATE_DATA,
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MIPS_BOOT_DATA,
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MIPS_STACK,
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RISCV_UNCACHED_CODE,
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RISCV_CACHED_CODE,
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RISCV_PRIVATE_DATA,
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RISCV_COREMEM_CODE,
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RISCV_COREMEM_DATA,
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};
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enum pvr_fw_section_type {
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NONE = 0,
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FW_CODE,
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FW_DATA,
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FW_COREMEM_CODE,
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FW_COREMEM_DATA,
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};
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/*
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* FW binary format with FW info attached:
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*
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* Contents Offset
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* +-----------------+
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* | | 0
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* | |
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* | Original binary |
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* | file |
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* | (.ldr/.elf) |
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* | |
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* | |
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* +-----------------+
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* | Device info | FILE_SIZE - 4K - device_info_size
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* +-----------------+
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* | FW info header | FILE_SIZE - 4K
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* +-----------------+
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* | |
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* | FW layout table |
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* | |
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* +-----------------+
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* FILE_SIZE
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*/
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#define PVR_FW_INFO_VERSION 3
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#define PVR_FW_FLAGS_OPEN_SOURCE BIT(0)
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/** struct pvr_fw_info_header - Firmware header */
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struct pvr_fw_info_header {
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/** @info_version: FW info header version. */
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u32 info_version;
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/** @header_len: Header length. */
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u32 header_len;
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/** @layout_entry_num: Number of entries in the layout table. */
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u32 layout_entry_num;
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/** @layout_entry_size: Size of an entry in the layout table. */
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u32 layout_entry_size;
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/** @bvnc: GPU ID supported by firmware. */
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aligned_u64 bvnc;
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/** @fw_page_size: Page size of processor on which firmware executes. */
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u32 fw_page_size;
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/** @flags: Compatibility flags. */
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u32 flags;
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/** @fw_version_major: Firmware major version number. */
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u16 fw_version_major;
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/** @fw_version_minor: Firmware minor version number. */
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u16 fw_version_minor;
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/** @fw_version_build: Firmware build number. */
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u32 fw_version_build;
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/** @device_info_size: Size of device info structure. */
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u32 device_info_size;
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/** @padding: Padding. */
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u32 padding;
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};
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/**
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* struct pvr_fw_layout_entry - Entry in firmware layout table, describing a
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* section of the firmware image
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*/
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struct pvr_fw_layout_entry {
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/** @id: Section ID. */
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enum pvr_fw_section_id id;
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/** @type: Section type. */
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enum pvr_fw_section_type type;
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/** @base_addr: Base address of section in FW address space. */
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u32 base_addr;
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/** @max_size: Maximum size of section, in bytes. */
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u32 max_size;
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/** @alloc_size: Allocation size of section, in bytes. */
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u32 alloc_size;
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/** @alloc_offset: Allocation offset of section. */
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u32 alloc_offset;
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};
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/**
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* struct pvr_fw_device_info_header - Device information header.
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*/
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struct pvr_fw_device_info_header {
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/** @brn_mask_size: BRN mask size (in u64s). */
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u64 brn_mask_size;
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/** @ern_mask_size: ERN mask size (in u64s). */
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u64 ern_mask_size;
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/** @feature_mask_size: Feature mask size (in u64s). */
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u64 feature_mask_size;
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/** @feature_param_size: Feature parameter size (in u64s). */
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u64 feature_param_size;
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};
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#endif /* PVR_FW_INFO_H */
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