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189621726b
The clock controller also includes some reset lines. This patch implements a reset controller to assert and de-assert these resets. The reset controller itself is registered early (through CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot process (to start the secondary CPU cores). According to the public S805 datasheet there are two more reset bits in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by this patch (as these seem to be unused in Amlogic's vendor Linux kernel sources and their u-boot tree): - bit 15: GEN_DIV_SOFT_RESET - bit 14: SOFT_RESET All information was taken from the public S805 Datasheet and Amlogic's vendor GPL kernel sources. This patch is based on an earlier version submitted by Carlo Caione. Suggested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
21 lines
589 B
Text
21 lines
589 B
Text
config COMMON_CLK_AMLOGIC
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bool
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depends on OF
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depends on ARCH_MESON || COMPILE_TEST
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config COMMON_CLK_MESON8B
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bool
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depends on COMMON_CLK_AMLOGIC
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select RESET_CONTROLLER
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help
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Support for the clock controller on AmLogic S802 (Meson8),
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S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
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want peripherals and CPU frequency scaling to work.
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config COMMON_CLK_GXBB
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bool
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depends on COMMON_CLK_AMLOGIC
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select RESET_CONTROLLER
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help
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Support for the clock controller on AmLogic S905 devices, aka gxbb.
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Say Y if you want peripherals and CPU frequency scaling to work.
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