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Spill to DRAM functionality is a feature that allows STB (Smart Trace Buffer) to spill data from SRAM into DRAM on some future AMD ASICs. The size allocated for STB is more than the earlier SoC's which helps to collect more tracing and telemetry data. Co-developed-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20220204122527.3873552-1-Sanket.Goswami@amd.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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