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The IPC driver is used to send and receive messages to/from firmware running on the VPU. The only supported IPC message format is Job Submission Model (JSM) defined in vpu_jsm_api.h header. Co-developed-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com> Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com> Co-developed-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com> Signed-off-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20230117092723.60441-5-jacek.lawrynowicz@linux.intel.com
93 lines
2.4 KiB
C
93 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020-2023 Intel Corporation
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*/
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#ifndef __IVPU_IPC_H__
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#define __IVPU_IPC_H__
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include "vpu_jsm_api.h"
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struct ivpu_bo;
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/* VPU FW boot notification */
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#define IVPU_IPC_CHAN_BOOT_MSG 0x3ff
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#define IVPU_IPC_BOOT_MSG_DATA_ADDR 0x424f4f54
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/* The alignment to be used for IPC Buffers and IPC Data. */
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#define IVPU_IPC_ALIGNMENT 64
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#define IVPU_IPC_HDR_FREE 0
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#define IVPU_IPC_HDR_ALLOCATED 0
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/**
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* struct ivpu_ipc_hdr - The IPC message header structure, exchanged
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* with the VPU device firmware.
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* @data_addr: The VPU address of the payload (JSM message)
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* @data_size: The size of the payload.
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* @channel: The channel used.
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* @src_node: The Node ID of the sender.
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* @dst_node: The Node ID of the intended receiver.
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* @status: IPC buffer usage status
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*/
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struct ivpu_ipc_hdr {
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u32 data_addr;
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u32 data_size;
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u16 channel;
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u8 src_node;
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u8 dst_node;
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u8 status;
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} __packed __aligned(IVPU_IPC_ALIGNMENT);
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struct ivpu_ipc_consumer {
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struct list_head link;
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u32 channel;
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u32 tx_vpu_addr;
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u32 request_id;
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spinlock_t rx_msg_lock; /* Protects rx_msg_list */
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struct list_head rx_msg_list;
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wait_queue_head_t rx_msg_wq;
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};
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struct ivpu_ipc_info {
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struct gen_pool *mm_tx;
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struct ivpu_bo *mem_tx;
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struct ivpu_bo *mem_rx;
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atomic_t rx_msg_count;
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spinlock_t cons_list_lock; /* Protects cons_list */
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struct list_head cons_list;
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atomic_t request_id;
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struct mutex lock; /* Lock on status */
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bool on;
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};
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int ivpu_ipc_init(struct ivpu_device *vdev);
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void ivpu_ipc_fini(struct ivpu_device *vdev);
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void ivpu_ipc_enable(struct ivpu_device *vdev);
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void ivpu_ipc_disable(struct ivpu_device *vdev);
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void ivpu_ipc_reset(struct ivpu_device *vdev);
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int ivpu_ipc_irq_handler(struct ivpu_device *vdev);
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void ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
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u32 channel);
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void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons);
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int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
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struct ivpu_ipc_hdr *ipc_buf, struct vpu_jsm_msg *ipc_payload,
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unsigned long timeout_ms);
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int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
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enum vpu_ipc_msg_type expected_resp_type,
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struct vpu_jsm_msg *resp, u32 channel,
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unsigned long timeout_ms);
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#endif /* __IVPU_IPC_H__ */
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