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![Jacek Lawrynowicz](/assets/img/avatar_default.png)
VPU Memory Management Unit is based on ARM MMU-600. It allows the creation of multiple virtual address spaces for the device and map noncontinuous host memory (there is no dedicated memory on the VPU). Address space is implemented as a struct ivpu_mmu_context, it has an ID, drm_mm allocator for VPU addresses and struct ivpu_mmu_pgtable that holds actual 3-level, 4KB page table. Context with ID 0 (global context) is created upon driver initialization and it's mainly used for mapping memory required to execute the firmware. Contexts with non-zero IDs are user contexts allocated each time the devices is open()-ed and they map command buffers and other workload-related memory. Workloads executing in a given contexts have access only to the memory mapped in this context. This patch is has two main files: - ivpu_mmu_context.c handles MMU page tables and memory mapping - ivpu_mmu.c implements a driver that programs the MMU device Co-developed-by: Karol Wachowski <karol.wachowski@linux.intel.com> Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com> Co-developed-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com> Signed-off-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20230117092723.60441-3-jacek.lawrynowicz@linux.intel.com
50 lines
1.6 KiB
C
50 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020-2023 Intel Corporation
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*/
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#ifndef __IVPU_MMU_CONTEXT_H__
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#define __IVPU_MMU_CONTEXT_H__
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#include <drm/drm_mm.h>
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struct ivpu_device;
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struct ivpu_file_priv;
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struct ivpu_addr_range;
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#define IVPU_MMU_PGTABLE_ENTRIES 512
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struct ivpu_mmu_pgtable {
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u64 **pgd_cpu_entries[IVPU_MMU_PGTABLE_ENTRIES];
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u64 *pgd_entries[IVPU_MMU_PGTABLE_ENTRIES];
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u64 *pgd;
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dma_addr_t pgd_dma;
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};
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struct ivpu_mmu_context {
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struct mutex lock; /* protects: mm, pgtable, bo_list */
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struct drm_mm mm;
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struct ivpu_mmu_pgtable pgtable;
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struct list_head bo_list;
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u32 id;
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};
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int ivpu_mmu_global_context_init(struct ivpu_device *vdev);
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void ivpu_mmu_global_context_fini(struct ivpu_device *vdev);
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int ivpu_mmu_user_context_init(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u32 ctx_id);
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void ivpu_mmu_user_context_fini(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx);
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void ivpu_mmu_user_context_mark_invalid(struct ivpu_device *vdev, u32 ssid);
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int ivpu_mmu_context_insert_node_locked(struct ivpu_mmu_context *ctx,
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const struct ivpu_addr_range *range,
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u64 size, struct drm_mm_node *node);
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void ivpu_mmu_context_remove_node_locked(struct ivpu_mmu_context *ctx,
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struct drm_mm_node *node);
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int ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
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u64 vpu_addr, struct sg_table *sgt, bool llc_coherent);
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void ivpu_mmu_context_unmap_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
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u64 vpu_addr, struct sg_table *sgt);
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#endif /* __IVPU_MMU_CONTEXT_H__ */
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