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393fc2f594
pci1xxxx is a PCIe switch with a multi-function endpoint on one of its downstream ports. PIO function is one of the functions in the multi-function endpoint. PIO function combines a GPIO controller and also an interface to program pci1xxxx's OTP & EEPROM. This auxiliary bus driver is loaded for the PIO function and separate child devices are enumerated for GPIO controller and OTP/EEPROM interface. Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com> Link: https://lore.kernel.org/r/20220824200047.150308-2-kumaravel.thiagarajan@microchip.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
28 lines
640 B
C
28 lines
640 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2022 Microchip Technology Inc. */
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#ifndef _GPIO_PCI1XXXX_H
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#define _GPIO_PCI1XXXX_H
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/kthread.h>
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#include <linux/types.h>
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#include <linux/auxiliary_bus.h>
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/* Perform operations like variable length write, read and write with read back for OTP / EEPROM
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* Perform bit mode write in OTP
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*/
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struct gp_aux_data_type {
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int irq_num;
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resource_size_t region_start;
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resource_size_t region_length;
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};
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struct auxiliary_device_wrapper {
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struct auxiliary_device aux_dev;
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struct gp_aux_data_type gp_aux_data;
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};
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#endif
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