mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 10:49:33 +00:00
![Kumaravel Thiagarajan](/assets/img/avatar_default.png)
build errors listed below and reported by Sudip Mukherjee
<sudipm.mukherjee@gmail.com> for the builds of
riscv, s390, csky, alpha and loongarch allmodconfig are fixed in
this patch.
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c:311:12: error: 'pci1xxxx_gpio_resume' defined but not used [-Werror=unused-function]
311 | static int pci1xxxx_gpio_resume(struct device *dev)
| ^~~~~~~~~~~~~~~~~~~~
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c:295:12: error: 'pci1xxxx_gpio_suspend' defined but not used [-Werror=unused-function]
295 | static int pci1xxxx_gpio_suspend(struct device *dev)
| ^~~~~~~~~~~~~~~~~~~~~
Fixes: 4ec7ac90ff
("misc: microchip: pci1xxxx: Add power management functions - suspend & resume handlers.")
Reported-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
Link: https://lore.kernel.org/r/20220915094729.646185-1-kumaravel.thiagarajan@microchip.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
427 lines
13 KiB
C
427 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2022 Microchip Technology Inc.
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// pci1xxxx gpio driver
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/gpio/driver.h>
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#include <linux/bio.h>
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#include <linux/mutex.h>
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#include <linux/kthread.h>
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#include <linux/interrupt.h>
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#include "mchp_pci1xxxx_gp.h"
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#define PCI1XXXX_NR_PINS 93
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#define PERI_GEN_RESET 0
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#define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400)
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#define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10)
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#define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20)
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#define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30)
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#define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40)
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#define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50)
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#define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60)
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#define WAKEMASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x70)
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#define MODE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x80)
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#define INTR_LO_TO_HI_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0x90)
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#define INTR_HI_TO_LO_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0xA0)
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#define INTR_LEVEL_CONFIG_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xB0)
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#define INTR_LEVEL_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xC0)
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#define INTR_STAT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xD0)
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#define DEBOUNCE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xE0)
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#define PIO_GLOBAL_CONFIG_OFFSET (0x400 + 0xF0)
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#define PIO_PCI_CTRL_REG_OFFSET (0x400 + 0xF4)
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#define INTR_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x100)
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#define INTR_STATUS_OFFSET(x) (((x) * 4) + 0x400 + 0xD0)
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struct pci1xxxx_gpio {
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struct auxiliary_device *aux_dev;
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void __iomem *reg_base;
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struct gpio_chip gpio;
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spinlock_t lock;
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int irq_base;
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};
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static int pci1xxxx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
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{
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struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
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u32 data;
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int ret = -EINVAL;
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data = readl(priv->reg_base + INP_EN_OFFSET(nr));
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if (data & BIT(nr % 32)) {
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ret = 1;
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} else {
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data = readl(priv->reg_base + OUT_EN_OFFSET(nr));
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if (data & BIT(nr % 32))
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ret = 0;
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}
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return ret;
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}
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static inline void pci1xxx_assign_bit(void __iomem *base_addr, unsigned int reg_offset,
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unsigned int bitpos, bool set)
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{
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u32 data;
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data = readl(base_addr + reg_offset);
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if (set)
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data |= BIT(bitpos);
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else
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data &= ~BIT(bitpos);
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writel(data, base_addr + reg_offset);
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}
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static int pci1xxxx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
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{
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struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true);
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pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int pci1xxxx_gpio_get(struct gpio_chip *gpio, unsigned int nr)
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{
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struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
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return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1;
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}
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static int pci1xxxx_gpio_direction_output(struct gpio_chip *gpio,
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unsigned int nr, int val)
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{
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struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
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unsigned long flags;
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u32 data;
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spin_lock_irqsave(&priv->lock, flags);
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pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false);
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pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true);
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data = readl(priv->reg_base + OUT_OFFSET(nr));
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if (val)
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data |= (1 << (nr % 32));
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else
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data &= ~(1 << (nr % 32));
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writel(data, priv->reg_base + OUT_OFFSET(nr));
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static void pci1xxxx_gpio_set(struct gpio_chip *gpio,
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unsigned int nr, int val)
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{
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struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static int pci1xxxx_gpio_set_config(struct gpio_chip *gpio, unsigned int offset,
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unsigned long config)
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{
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struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
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unsigned long flags;
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int ret = 0;
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spin_lock_irqsave(&priv->lock, flags);
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switch (pinconf_to_config_param(config)) {
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case PIN_CONFIG_BIAS_PULL_UP:
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pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true);
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true);
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false);
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pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false);
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true);
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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return ret;
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}
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static void pci1xxxx_gpio_irq_ack(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
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unsigned int gpio = irqd_to_hwirq(data);
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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pci1xxx_assign_bit(priv->reg_base, INTR_STAT_OFFSET(gpio), (gpio % 32), true);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void pci1xxxx_gpio_irq_set_mask(struct irq_data *data, bool set)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
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unsigned int gpio = irqd_to_hwirq(data);
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void pci1xxxx_gpio_irq_mask(struct irq_data *data)
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{
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pci1xxxx_gpio_irq_set_mask(data, true);
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}
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static void pci1xxxx_gpio_irq_unmask(struct irq_data *data)
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{
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pci1xxxx_gpio_irq_set_mask(data, false);
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}
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static int pci1xxxx_gpio_set_type(struct irq_data *data, unsigned int trigger_type)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
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unsigned int gpio = irqd_to_hwirq(data);
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unsigned int bitpos = gpio % 32;
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if (trigger_type & IRQ_TYPE_EDGE_FALLING) {
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pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
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bitpos, false);
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pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio),
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bitpos, false);
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irq_set_handler_locked(data, handle_edge_irq);
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} else {
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pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
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bitpos, true);
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}
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if (trigger_type & IRQ_TYPE_EDGE_RISING) {
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pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
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bitpos, false);
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pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
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false);
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irq_set_handler_locked(data, handle_edge_irq);
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} else {
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pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
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bitpos, true);
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}
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if (trigger_type & IRQ_TYPE_LEVEL_LOW) {
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pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
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bitpos, true);
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pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
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bitpos, false);
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pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
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true);
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irq_set_handler_locked(data, handle_edge_irq);
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}
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if (trigger_type & IRQ_TYPE_LEVEL_HIGH) {
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pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
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bitpos, false);
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pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
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bitpos, false);
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pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
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true);
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irq_set_handler_locked(data, handle_edge_irq);
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}
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if ((!(trigger_type & IRQ_TYPE_LEVEL_LOW)) && (!(trigger_type & IRQ_TYPE_LEVEL_HIGH)))
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pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true);
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return true;
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}
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static irqreturn_t pci1xxxx_gpio_irq_handler(int irq, void *dev_id)
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{
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struct pci1xxxx_gpio *priv = dev_id;
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struct gpio_chip *gc = &priv->gpio;
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unsigned long int_status = 0;
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unsigned long flags;
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u8 pincount;
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int bit;
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u8 gpiobank;
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spin_lock_irqsave(&priv->lock, flags);
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pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true);
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spin_unlock_irqrestore(&priv->lock, flags);
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for (gpiobank = 0; gpiobank < 3; gpiobank++) {
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spin_lock_irqsave(&priv->lock, flags);
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int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
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spin_unlock_irqrestore(&priv->lock, flags);
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if (gpiobank == 2)
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pincount = 29;
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else
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pincount = 32;
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for_each_set_bit(bit, &int_status, pincount) {
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unsigned int irq;
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spin_lock_irqsave(&priv->lock, flags);
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writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
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spin_unlock_irqrestore(&priv->lock, flags);
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irq = irq_find_mapping(gc->irq.domain, (bit + (gpiobank * 32)));
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generic_handle_irq(irq);
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}
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}
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spin_lock_irqsave(&priv->lock, flags);
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pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false);
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spin_unlock_irqrestore(&priv->lock, flags);
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return IRQ_HANDLED;
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}
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static struct irq_chip pci1xxxx_gpio_irqchip = {
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.name = "pci1xxxx_gpio",
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.irq_ack = pci1xxxx_gpio_irq_ack,
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.irq_mask = pci1xxxx_gpio_irq_mask,
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.irq_unmask = pci1xxxx_gpio_irq_unmask,
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.irq_set_type = pci1xxxx_gpio_set_type,
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};
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static int pci1xxxx_gpio_suspend(struct device *dev)
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{
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struct pci1xxxx_gpio *priv = dev_get_drvdata(dev);
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
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16, true);
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pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
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17, false);
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pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int pci1xxxx_gpio_resume(struct device *dev)
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{
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struct pci1xxxx_gpio *priv = dev_get_drvdata(dev);
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
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17, true);
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pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
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16, false);
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pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int pci1xxxx_gpio_setup(struct pci1xxxx_gpio *priv, int irq)
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{
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struct gpio_chip *gchip = &priv->gpio;
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struct gpio_irq_chip *girq;
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int retval;
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gchip->label = dev_name(&priv->aux_dev->dev);
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gchip->parent = &priv->aux_dev->dev;
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gchip->owner = THIS_MODULE;
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gchip->direction_input = pci1xxxx_gpio_direction_input;
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gchip->direction_output = pci1xxxx_gpio_direction_output;
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gchip->get_direction = pci1xxxx_gpio_get_direction;
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gchip->get = pci1xxxx_gpio_get;
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gchip->set = pci1xxxx_gpio_set;
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gchip->set_config = pci1xxxx_gpio_set_config;
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gchip->dbg_show = NULL;
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gchip->base = -1;
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gchip->ngpio = PCI1XXXX_NR_PINS;
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gchip->can_sleep = false;
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retval = devm_request_threaded_irq(&priv->aux_dev->dev, irq,
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NULL, pci1xxxx_gpio_irq_handler,
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IRQF_ONESHOT, "PCI1xxxxGPIO", priv);
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if (retval)
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return retval;
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girq = &priv->gpio.irq;
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girq->chip = &pci1xxxx_gpio_irqchip;
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girq->parent_handler = NULL;
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girq->num_parents = 0;
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girq->parents = NULL;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_bad_irq;
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return 0;
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}
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static int pci1xxxx_gpio_probe(struct auxiliary_device *aux_dev,
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const struct auxiliary_device_id *id)
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{
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struct auxiliary_device_wrapper *aux_dev_wrapper;
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struct gp_aux_data_type *pdata;
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struct pci1xxxx_gpio *priv;
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int retval;
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aux_dev_wrapper = (struct auxiliary_device_wrapper *)
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container_of(aux_dev, struct auxiliary_device_wrapper, aux_dev);
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pdata = &aux_dev_wrapper->gp_aux_data;
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if (!pdata)
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return -EINVAL;
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priv = devm_kzalloc(&aux_dev->dev, sizeof(struct pci1xxxx_gpio), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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spin_lock_init(&priv->lock);
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priv->aux_dev = aux_dev;
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if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start, 0x800, aux_dev->name))
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return -EBUSY;
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priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800);
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if (!priv->reg_base)
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return -ENOMEM;
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writel(0x0264, (priv->reg_base + 0x400 + 0xF0));
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retval = pci1xxxx_gpio_setup(priv, pdata->irq_num);
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if (retval < 0)
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return retval;
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dev_set_drvdata(&aux_dev->dev, priv);
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return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv);
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_gpio_pm_ops, pci1xxxx_gpio_suspend, pci1xxxx_gpio_resume);
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static const struct auxiliary_device_id pci1xxxx_gpio_auxiliary_id_table[] = {
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{.name = "mchp_pci1xxxx_gp.gp_gpio"},
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{}
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};
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MODULE_DEVICE_TABLE(auxiliary, pci1xxxx_gpio_auxiliary_id_table);
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static struct auxiliary_driver pci1xxxx_gpio_driver = {
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.driver = {
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.name = "PCI1xxxxGPIO",
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.pm = &pci1xxxx_gpio_pm_ops,
|
|
},
|
|
.probe = pci1xxxx_gpio_probe,
|
|
.id_table = pci1xxxx_gpio_auxiliary_id_table
|
|
};
|
|
module_auxiliary_driver(pci1xxxx_gpio_driver);
|
|
|
|
MODULE_DESCRIPTION("Microchip Technology Inc. PCI1xxxx GPIO controller");
|
|
MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");
|
|
MODULE_LICENSE("GPL");
|