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3dad2344e9
The NAND command helpers tend to automatically shift the column address for x16 bus devices, since most commands expect a word address, not a byte address. The Read ID command, however, expects an 8-bit address (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or 0x20). This fixes the column address for a few drivers which imitate the nand_base defaults. Note that I don't touch sh_flctl.c, since it already handles this problem slightly differently (note its comment "READID is always performed using an 8-bit bus"). I have not tested this patch, as I only have x8 parts up for testing at this point. Hopefully that can change soon... Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-By: Pekon Gupta <pekon@ti.com> |
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| .. | ||
| bbm.h | ||
| blktrans.h | ||
| cfi.h | ||
| cfi_endian.h | ||
| concat.h | ||
| doc2000.h | ||
| flashchip.h | ||
| fsmc.h | ||
| ftl.h | ||
| gen_probe.h | ||
| inftl.h | ||
| latch-addr-flash.h | ||
| lpc32xx_mlc.h | ||
| lpc32xx_slc.h | ||
| map.h | ||
| mtd.h | ||
| mtdram.h | ||
| nand-gpio.h | ||
| nand.h | ||
| nand_bch.h | ||
| nand_ecc.h | ||
| ndfc.h | ||
| nftl.h | ||
| onenand.h | ||
| onenand_regs.h | ||
| partitions.h | ||
| pfow.h | ||
| physmap.h | ||
| pismo.h | ||
| plat-ram.h | ||
| qinfo.h | ||
| sh_flctl.h | ||
| sharpsl.h | ||
| spear_smi.h | ||
| super.h | ||
| ubi.h | ||
| xip.h | ||