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f10ee3dcc9
The switch to the user space page tables in the low level ASM code sets
unconditionally bit 12 and bit 11 of CR3. Bit 12 is switching the base
address of the page directory to the user part, bit 11 is switching the
PCID to the PCID associated with the user page tables.
This fails on a machine which lacks PCID support because bit 11 is set in
CR3. Bit 11 is reserved when PCID is inactive.
While the Intel SDM claims that the reserved bits are ignored when PCID is
disabled, the AMD APM states that they should be cleared.
This went unnoticed as the AMD APM was not checked when the code was
developed and reviewed and test systems with Intel CPUs never failed to
boot. The report is against a Centos 6 host where the guest fails to boot,
so it's not yet clear whether this is a virt issue or can happen on real
hardware too, but thats irrelevant as the AMD APM clearly ask for clearing
the reserved bits.
Make sure that on non PCID machines bit 11 is not set by the page table
switching code.
Andy suggested to rename the related bits and masks so they are clearly
describing what they should be used for, which is done as well for clarity.
That split could have been done with alternatives but the macro hell is
horrible and ugly. This can be done on top if someone cares to remove the
extra orq. For now it's a straight forward fix.
Fixes: 6fd166aae7 ("x86/mm: Use/Fix PCID to optimize user/kernel switches")
Reported-by: Laura Abbott <labbott@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: stable <stable@vger.kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Willy Tarreau <w@1wt.eu>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801140009150.2371@nanos
56 lines
1.7 KiB
C
56 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_PROCESSOR_FLAGS_H
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#define _ASM_X86_PROCESSOR_FLAGS_H
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#include <uapi/asm/processor-flags.h>
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#include <linux/mem_encrypt.h>
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#ifdef CONFIG_VM86
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#define X86_VM_MASK X86_EFLAGS_VM
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#else
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#define X86_VM_MASK 0 /* No VM86 support */
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#endif
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/*
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* CR3's layout varies depending on several things.
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*
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* If CR4.PCIDE is set (64-bit only), then CR3[11:0] is the address space ID.
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* If PAE is enabled, then CR3[11:5] is part of the PDPT address
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* (i.e. it's 32-byte aligned, not page-aligned) and CR3[4:0] is ignored.
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* Otherwise (non-PAE, non-PCID), CR3[3] is PWT, CR3[4] is PCD, and
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* CR3[2:0] and CR3[11:5] are ignored.
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*
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* In all cases, Linux puts zeros in the low ignored bits and in PWT and PCD.
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*
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* CR3[63] is always read as zero. If CR4.PCIDE is set, then CR3[63] may be
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* written as 1 to prevent the write to CR3 from flushing the TLB.
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*
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* On systems with SME, one bit (in a variable position!) is stolen to indicate
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* that the top-level paging structure is encrypted.
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*
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* All of the remaining bits indicate the physical address of the top-level
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* paging structure.
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*
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* CR3_ADDR_MASK is the mask used by read_cr3_pa().
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*/
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#ifdef CONFIG_X86_64
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/* Mask off the address space ID and SME encryption bits. */
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#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull)
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#define CR3_PCID_MASK 0xFFFull
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#define CR3_NOFLUSH BIT_ULL(63)
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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# define X86_CR3_PTI_PCID_USER_BIT 11
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#endif
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#else
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/*
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* CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
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* a tiny bit of code size by setting all the bits.
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*/
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#define CR3_ADDR_MASK 0xFFFFFFFFull
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#define CR3_PCID_MASK 0ull
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#define CR3_NOFLUSH 0
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#endif
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#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
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